DS2196 Dallas Semiconducotr, DS2196 Datasheet - Page 47

• Manufacturer Part Number: DS2196
• Description: T1 Dual Framer LIU
• Manufacturer: Dallas Semiconducotr

CCR5B: COMMON CONTROL REGISTER 5 FRAMER B (Address = B9 Hex)
CCR6A: COMMON CONTROL REGISTER 6 FRAMER A (Address = 1E Hex)
CCR6B: COMMON CONTROL REGISTER 6 FRAMER B (Address = BE Hex)
(MSB)
(MSB)
RJC
TJC
SYMBOL
SYMBOL
MECU
EAMS
TCM4
TCM3
TCM2
TCM1
TCM0
RCM4
RCM3
RCM2
RCM1
RCM0
RJC
TJC
–
–
EAMS
–
POSITION
POSITION
CCR6A.7
CCR6A.6
CCR6A.5
CCR6A.4
CCR6A.3
CCR6A.2
CCR6A.1
CCR6A.0
CCR5B.7
CCR5B.6
CCR5B.5
CCR5B.4
CCR5B.3
CCR5B.2
CCR5B.1
CCR5B.0
MECU
–
NAME AND DESCRIPTION
NAME AND DESCRIPTION
Transmit Japanese CRC6 Enable.
0 = use ANSI/AT&T/ITU CRC6 calculation (normal operation)
1 = use Japanese standard JT–G704 CRC6 calculation
Not Assigned. Must be set to 0 when written.
Not Assigned. Must be set to 0 when written.
Transmit Channel Monitor Bit 4. MSB of a channel decode
that determines which transmit channel data will appear in the
TDS0M register. See Section 10 for details.
Transmit Channel Monitor Bit 3.
Transmit Channel Monitor Bit 2.
Transmit Channel Monitor Bit 1.
Transmit Channel Monitor Bit 0. LSB of the channel
decode.
Receive Japanese CRC6 Enable.
0 = use ANSI/AT&T/ITU CRC6 calculation (normal operation)
1 = use Japanese standard JT–G704 CRC6 calculation
Error Accumulation Mode Select.
0 = CCR3A.2 determines accumulation time
1 = CCR6A.5 determines accumulation time
Manual Error Counter Update. When enabled by CCR6A.6,
the changing of this bit from a 0 to a 1 allows the next clock
cycle to load the error counter registers with the latest counts
and reset the counters. The user must wait a minimum of 972
ns (1.5 clock periods) before reading the error count registers to
allow for proper update.
Receive Channel Monitor Bit 4. MSB of a channel decode
that determines which receive channel data will appear in the
RDS0M register. See Section 10 for details.
Receive Channel Monitor Bit 3.
Receive Channel Monitor Bit 2.
Receive Channel Monitor Bit 1.
Receive Channel Monitor Bit 0. LSB of the channel decode.
RCM4
TCM4
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RCM3
TCM3
TCM2
RCM2
TCM1
RCM1
RCM0
TCM0
(LSB)
(LSB)
DS2196