AN1525 STMicroelectronics, AN1525 Datasheet

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AN1525

Manufacturer Part Number
AN1525
Description
I2C COMMUNICATION BETWEEN ST52X520 AND EEPROM
Manufacturer
STMicroelectronics
Datasheet
AN1525
APPLICATION NOTE
2
I
C Communication between ST52x520 and EEPROM
Author: C.Ruggieri
1 INTRODUCTION
2
This AN shows an example of how to interface style I
C EEPROM with an ST52x520 microcontroller using
2
an I
C protocol. An ST24C04 (4Kbit) memory is used for this example, although similar thoughts are also
2
true for any other type of EEPROM that uses an I
C bus.
The software that is proposed uses a read/write routine that performs random access to a certain number
of user defined EEPROM memory locations with the ST52x520 microcontroller configured in master
mode.
2 COMMUNICATION PROTOCOL
2
The I
C standard protocol defines every device that sends data in the bus as a “transmitter” and every
device that reads data as “receiver”.
The device that controls data transfer is defined as “master”, while all the others are defined as “slave”.
2
The standard I
C protocol uses a bidirectional data line (SDA) and a clock line (SCL) generated by the
master device, which in this specific case has to necessarily be the microcontroller, since EEPROM only
works as slave.
Start Conditon: Start is recognized when the SDA line switches from HIGH to LOW, while the SCL line
is stable in HIGH state. START has to precede every data transfer command.
Stop Condition: Stop is recognized when the SDA line switches from HIGH to LOW during a stable phase
of the SCL line in HIGH state. The stop condition ends communication.
Acknowledge Bit (ACK): The ACK signal is used to indicate that the data transfer was successful. The
“bus transmitter’” (both master and slave) will release the SDA line after having sent an 8 bit byte. During
the 9th clock cycles, the “receiver” places the SDA line in LOW in order to indicate that it has received the
8 bits of data.
EEPROM Addressing: In order to begin the communication between the “bus master” and the “slave”
memory, the master has to begin with a START condition. Afterwards, the master serially sends 8 bits to
the SDA line (MSB the first), which corresponds to the Device Select Code (7 bits) and to one READ or
WRITE bit. The Device Select Code is composed of the first four bits equal to 1010 (unique device iden-
2
tification code), which correspond to the specifications of the I
C protocol. The three successive bits iden-
tify the chip enable inputs that allow the same bus to interface with other memories.
2
Figure 1. I
C BUS PROTOCOL
April 2002
1/12

Related parts for AN1525

AN1525 Summary of contents

Page 1

... I tify the chip enable inputs that allow the same bus to interface with other memories. 2 Figure BUS PROTOCOL April 2002 APPLICATION NOTE 2 C EEPROM with an ST52x520 microcontroller using 2 C bus protocol. The three successive bits iden- AN1525 Author: C.Ruggieri 1/12 ...

Page 2

... AN1525 - APPLICATION NOTE 3 HARDWARE DESCRIPTION The electrical schematic of the circuit, which the proposed program refers to is shown in Figure 2. The Pa0/SCL pin of the microcontroller is connected to the SCL line and the PA1/SDA pin is connected with the SDA line for bus synchronization. The pushbutton is connected with pin PA7 (external interrupt, INT) in order to select the reading and writing phase ...

Page 3

... ST24C04. The software is developed with Visual FIVE and allows sequential writing of a maximum of 8 bytes (for ST24C04 certain memory address and the reading, afterwards, of the same amount of bytes. The software that is proposed can be found in file I2CGP.FS4 (see file AN1525.FS4 in the applica- tion note page at the following web site: http://www.st.com/five ). ...

Page 4

... AN1525 - APPLICATION NOTE In the example that has been proposed, bit b1 (that represents bit A8 of the memory address) wasn’t used in the Device Select Code. The user can select only one range of addresses, which range from 0 to 255. In order to address memory locations that exceed the quantity indicated, the program has to be modified. ...

Page 5

... ST52x520 datasheet for the complete diagram of the sequences, relative to the I crocontroller). Figure 8. 7 BIT MASTER TRANSFER SEQUENCING AN1525 - APPLICATION NOTE 2 C peripheral and afterwards enables the pe interrupt routine. ...

Page 6

... AN1525 - APPLICATION NOTE Figure 9. EXTERNAL INTERRUPT WINDOW 2 4 Interrupt Window The routine of the interrupt window of the I that are necessary for the correct reading and writing sequence. As can be seen in Figure 8, each time a START condition begins or data begins, the I quest that will have to be managed by the user (EVx events). ...

Page 7

... FLAG register, control will pass to the conditional block BTF10, which determines if the operation to be performed is that of reading or writing (operation which is established by the value of bit 0 of the FLAG register, modified with every exterted pressure on the pushbutton). AN1525 - APPLICATION NOTE 2 C peripheral will not continue operations requested if ...

Page 8

... AN1525 - APPLICATION NOTE 4.2.2 Writing Block. If writing performed, the program will execute the instructions of the block shown in Figure 12 (bit 0 of the FLAG register = 0). The conditional Buffer block verifies when the number of bytes sent from the peripheral of the ST52x520 microcontroller to the memory has achieved the number of bytes indicated by the user in the BYTE_N variable ...

Page 9

... Once the BTF10 block condition is performed, seeing that bit0 of register FLAG is set to ‘1’, the program will perform the reading block represented by Figure 14. Figure 14. READ FLOW BLOCKS C routine. After each START, bit 0 of the SR1 register is set to ‘1’ and the AN1525 - APPLICATION NOTE 9/12 ...

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... AN1525 - APPLICATION NOTE The first conditional block (R_ _or_W) verifies if bit 3 of the FLAG register has already been set to ‘1’. In case it is negative, the routine sets this bit to ‘1’ and sends the START condition, exiting immediately after 2 the I C routine via the Retl1 control. ...

Page 11

... The PC3 signal chang- es state before sending or receiving every byte of data from the memory. Lastly, the PC4 signal changes state everytime the STOP condition is sent. REFERENCES [1] ST52x520 - Datasheet, STMicroelectronics, 2001 [2] ST24C0Z1 - Datasheet, STMicroelectronics, 1999 [3] Visual FIVE 5.0 - User Manual, STMicroelectronics, 2002 AN1525 - APPLICATION NOTE 11/12 ...

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... AN1525 - APPLICATION NOTE Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice ...

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