AN1525 STMicroelectronics, AN1525 Datasheet - Page 10

• Manufacturer Part Number: AN1525
• Description: I2C COMMUNICATION BETWEEN ST52X520 AND EEPROM
• Manufacturer: STMicroelectronics

AN1525 - APPLICATION NOTE
The first conditional block (R_ _or_W) verifies if bit 3 of the FLAG register has already been set to ‘1’. In
case it is negative, the routine sets this bit to ‘1’ and sends the START condition, exiting immediately after
the I
When the START condition has been generated by the peripheral, the microcontroller will generate an in-
terrupt, which will allow the program to perform the ADD_or_R conditional block, seeing that at every
START bit, b0 of the SR1 register is set to ‘1’.
This time, seeing that bit 3 of the FLAG register is set to ‘1’, the program will perform the Read block, which
via the CB_W control will send the Device Select Code to the memory with the RW bit set to ‘1’ (see Figure
10). At the end of the transmission of the I
this point, two operations will have to be performed: reading the SR1 register (operation performed every-
time the I
per the specifications of the I2C peripheral that are found on the ST52x520 microcontroller datasheet.
It’s important to notice that as soon as the SET_Fb1_CR block writes on the CR register, the I
immediately begins to generate the clock signals on the SCL line to receive data, generating a second
interrupt. Only at this time may the receiving register be read through the R_DR control. If reading occurs
immediately after writing on the CR register (before the peripheral completes reading data), the micro
would return the value previously memorized in the Data Register (DR) of the I
example, is the value of the Device Select Code with the RW bit set to ‘1’ (A1h).
This is the reason why bit 1 of the register FLAG was used: when this bit is reset to ‘0’, it means that the
routine is serving an interrupt generated, following the completion of the Device Select Code being sent
with the RW bit set to ‘1’. The INT_CB condition becomes true and the program follows the SET_Fb1_CR
block, exiting the I
soon as the peripheral has finished receiving the first data and the data is ready in the reading register DR
of the I
Window will restart from the conditional block NO_ACK, since at this point bit 1 of the FLAG register is set
to ‘1’.
Two conditional blocks are present in the program flow of data reception (as shown in Figure 14), which
verify the transmission both of the next to last and of the last data. This is necessary seeing that the mi-
crocontroller wont have to generate the ACK after receiving the last data, in order to allow the memory to
close communication. This control is performed by the conditional block NO_ACK which, when index i (this
index specifies the number of bytes that have already been sent) achieves the value of variable k (=BufL-
1), it inhibits the generation of the Acknowledgement via the instructions CR =_cnfReg_16 and
_cnfReg_16 = CR & 251 of the NO_ACK_G block, resetting bit 2 (=ACK) of the Control Register (CR) of
the I
Instead, the second conditional Buffer block (2) verifies reading of the last byte by performing a confron-
tation of the index with variable p, and in case it is positive it generates a STOP condition before reading
the last data byte that is sent, via the R_DR control.
The use of the two variables k and p is necessary in this program in order to anticipate if the user wants
to write or read only one data, which in this case, ACK inhibition and the STOP condition must be sent
contemporaneously. If the value of BYTE_N is equal to 1, both the variable p and k will have the value 0
(see Figure 6) and both conditions of the two conditional blocks NO_ACK and Buffer (2) will be true.
Finally, the Snd_PB1_i block allows data read by the memory to be sent to port B of the ST52x520 micro-
controller and increments the value of the index variable i.
After receiving the last byte and before exiting the interrupt routine via the Retl1 condtion, the program
returns to the initial conditions of the bit in the FLAG register in order to retransmit or be able to receive
once again via the Re-INIT (1) block (as represented in Figure 13).
10/12
2
2
C routine via the Retl1 control.
C peripheral of the ST52x520 microcontroller to ‘0’.
2
C peripheral of the microcontroller, a second interrupt is generated. The program within the I2C
2
C is called by the RD_SR1_SR2 block) and writing on the CR register (for example PE=1), as
2
C routine via the Retl1 control, right after having set bit 1 of the FLAG register to ‘1’. As
2
C peripheral, the microcontroller will generate an interrupt. At
2
C peripheral, which in this
2
C peripheral