AN1525 STMicroelectronics, AN1525 Datasheet - Page 7

• Manufacturer Part Number: AN1525
• Description: I2C COMMUNICATION BETWEEN ST52X520 AND EEPROM
• Manufacturer: STMicroelectronics

AN1525 - APPLICATION NOTE
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This operation is indispensable, seeing that the I
C peripheral will not continue operations requested if
SR1 is not read. In fact, only by reading this register the microcontroller resets the Event Flag bit (EVF) to
‘0’.
The first conditional block (SB) verifies if the START condition was just generated. In fact, bit 0 of register
SR1 is set to ‘1’ only after a START condition.
When an interrupt is generated following a START condition, the program verifies if START is the initial
one, or the one that follows the address location where to begin reading (Random Address Read Mode,
see Figure 4). In this last case, bit 3 of the FLAG register will be set to ‘1’, otherwise it will be reset to ‘0’.
When the first START occurs, the value transferred to the I2CData (used by the program to transfer data
to/from memory via the Send and Receive controls of Visual FIVE) will be 160 (corresponding to the value
of the Select Code with bit 7 - RW - reset to ‘0’ for writing operations) if bit 3 of the register FLAG is ‘0’.
The address transferred to the variable SlaveADD will be that of writing, W_ADD. If, on the other hand, bit
3 of FLAG register is ‘1’ (value that is modified after the second START has been sent), the value trans-
ferred to the I2CData register will be 161 (RW bit = ‘1’). Control is performed through the conditional block
ADD_or_R.
Figure 11. WRITE AND READ BLOCK WINDOWS
In case the START condition occurs after the initial address has been sent (in the Random Address Read
Mode), the program sets bit 2 of the FLAG register to ‘1’. This indicates that the Device Select Code for
reading has already been sent to the memory and from this point on, sequential reading may be per-
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formed. Lastly, the CB_W control transfers the I2CData variable to the I
C peripheral of the microcontroller
and the routine ends via the Retl1 control.
At the end of the process in which the contents of the I2CData have been sent to the memory, the micro-
controller will generate a new interrupt. However, bit 0 of register SR1 will be reset to ‘0’. The program will
examine the condition of the ADD_WR block, which verifies bit 2 of the FLAG register.
If this bit is still reset to ‘0’, the memory address to begin writing/reading data must be sent to the EE-
PROM. The I2C_ADD block transfers the value of the SlaveADD, which contains this address (address
previously transferred by the Write block, Figure 11) in the I2CData variable. In this phase, other than
reading the SR1 register, which is guaranteed by the RD_SR1_SR2 block performed at every entry of the
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interrupt of the I
C routine, writing on the Control Register (CR) of the I2C peripheral (see Figure 8, EV6)
is indespensable. This operation is performed by the WR_CR_Fb2 block via the CR=cnfReg_16
and_cnfReg_16=CR instructions, which simply read, then rewrite the CR register without modifications.
In this block, bit 2 of the FLAG register is set to ‘1’ in order to inform the program that the memory address
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where to read or write data was sent to EEPROM. After the address has been sent to the I
C peripheral
of the microcontroller (control W_SLAD), the routine terminates via the Retl1 control. At the end of the
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transfer process, the micro will generate a new interrupt and a new I
C routine will be called. This time,
due to a ‘1’ value of the bit 2 of the FLAG register, control will pass to the conditional block BTF10, which
determines if the operation to be performed is that of reading or writing (operation which is established by
the value of bit 0 of the FLAG register, modified with every exterted pressure on the pushbutton).
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