DS92LV1021 National Semiconductor, DS92LV1021 Datasheet - Page 11
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DS92LV1021
Manufacturer Part Number
DS92LV1021
Description
16-40 MHz 10 Bit Bus LVDS Serializer and Deserializer
Manufacturer
National Semiconductor
Datasheet
1.DS92LV1021.pdf
(18 pages)
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AC Timing Diagrams and Test Circuits
SW - Setup and Hold Time (Internal data sampling window)
t
t
V
Differential output signal is shown as (DO+)–(DO−), device in Data Transfer mode.
JIT
RSM
OD
- Serializer Output Bit Position Jitter
= (DO
= Receiver Sampling Margin Time
+
)–(DO
−
).
FIGURE 14. Deserializer PLL Lock Time from SyncPAT
FIGURE 15. Receiver Bus LVDS Input Skew Margin
11
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DS100110-16
DS100110-21
DS100110-22
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