DS92LV1021 National Semiconductor, DS92LV1021 Datasheet - Page 12

• Manufacturer Part Number: DS92LV1021
• Description: 16-40 MHz 10 Bit Bus LVDS Serializer and Deserializer
• Manufacturer: National Semiconductor

www.national.com
Application Information
Using the DS92LV1021 and DS92LV1210
The Serializer and Deserializer chipset is an easy to use
transmitter and receiver pair that sends 10 bits of parallel
TTL data over a serial Bus LVDS link up to 400 Mbps. Seri-
alization of the input data is accomplished using an onboard
PLL at the Serializer which embeds two clock bits with the
data. The Deserializer uses a separate reference clock
(REFCLK) and an onboard PLL to extract the clock informa-
tion from the incoming data stream and deserialize the data.
The Deserializer monitors the incoming clock information to
determine lock status and will indicate loss of lock by raising
the LOCK output.
Power Considerations
All CMOS design of the Serializer and Deserializer makes
them inherently low power devices. Additionally, the constant
current source nature of the Bus LVDS outputs minimize the
slope of the speed vs. I
Powering Up the Serializer
The DS92LV1021 must be powered up using a specific se-
quence to properly start the PLL up. Not following the se-
quence can cause the Bus LVDS outputs to be stuck in a
certain output state. This may occur if the TCLK input is
driven before power is applied to the Serializer. It is impor-
tant to note that this is not a latch up condition: no excessive
current is drawn by the Serializer in this state and the power
does not need to be cycled to recover from this state. Cycling
the PWRDWN pin from high to low and back to high will reset
the PLL and return the Serializer to normal operation.
To avoid this condition, the Serializer should be powered up
(ALL V
low for 1µs. Once the V
put can be driven and the Serializer will be ready for data
transmission.
Powering Up the Deserializer
The DS92LV1210 can be powered up at any time following
the proper sequence. The REFCLK input can be running be-
fore the Deserializer is powered up and it must be running in
order for the Deserializer to lock to incoming data. The Dese-
rializer outputs will remain in TRI-STATE
izer detects data transmission at its inputs and locks to the
incoming stream. The recommended power up sequence for
the deserializer is to power up all V
with the PWRDWN pin held low for 1µs. Once the V
have stabilized the Deserializer is ready for locking. Another
option to ensure proper power up is to cycle the PWRDWN
pin from high to low and back to high after power up.
Transmitting Data
Once the Serializer and Deserializer are powered up and
running they must be phase locked to each other in order to
transmit data. Phase locking is accomplished by the Serial-
izer sending SYNC patterns to the Deserializer. SYNC pat-
terns are sent by the Serializer whenever SYNC1 or SYNC2
inputs are held high. The LOCK output of the Deserializer is
high whenever the Deserializer is not locked. Connecting the
LOCK output of the Deserializer to one of the SYNC inputs of
the Serializer will guarantee that enough SYNC patterns are
sent to achieve Deserializer lock.
CC
pins) simultaneously with the PWRDWN pin held
CC
CC
pins have stabilized the TCLK in-
curve of CMOS designs.
CC
™
pins simultaneously
until the Deserial-
CC
pins
12
While the Deserializer LOCK output is low, data at the Dese-
rializer outputs (ROUT0-9) is valid except for the specific
case of loss of lock during transmission.