DS92LV1021 National Semiconductor, DS92LV1021 Datasheet - Page 13

• Manufacturer Part Number: DS92LV1021
• Description: 16-40 MHz 10 Bit Bus LVDS Serializer and Deserializer
• Manufacturer: National Semiconductor

Application Information
Noise Margin
The Deserializer noise margin is the amount of input jitter
(phase noise) that the Deserializer can tolerate and still reli-
ably receive data. Various environmental and systematic fac-
tors include:
out-of-band noise)
Recovering from LOCK Loss
In the case where the Serializer loses lock during data trans-
mission up to 5 cycles of data that was previously received
can be invalid. This is due to the delay in the lock detection
circuit. The lock detect circuit requires that invalid clock infor-
mation be received 4 times in a row to indicate loss of lock.
Since clock information has been lost it is possible that data
was also lost during these cycles. When the Deserializer
LOCK pin goes low, data from at least the previous 5 cycles
should be resent upon regaining lock.
Lock can be regained at the Deserializer by causing the Se-
rializer to resend SYNC patterns as described above.
PCB Considerations
The Bus LVDS devices Serializer and Deserializer should be
placed as close to the edge connector as possible. In mul-
tiple Deserializer applications, the distance from the Deseri-
Serializer: TCLK jitter, V
Media: ISI, V
Deserializer: V
CM
CC
noise
noise
CC
noise (noise bandwidth and
(Continued)
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alizer to the slot connector appears as a stub to the Serial-
izer driving the backplane traces. Longer stubs lower the
impedance of the bus increasing the load on the Serializer
and lowers threshold margin at the Deserializers. Deserial-
izer devices should be placed no more than 1 inch from the
slot connector.
Transmission Media
The Serializer and Deserializer are designed for data trans-
mission over a multi-drop bus. Multi-drop buses use a single
Serializer and multiple Deserializer devices. Since the Seri-
alizer can be driving from any point on the bus, the bus must
be terminated at both ends. For example, a 100 Ohm differ-
ential bus must be terminated at each end with 100 Ohms
lowering the DC impedance that the Serializer must drive to
50 Ohms. This load is further lowered by the addition of mul-
tiple Deserializers. Adding up to 20 Deserializers to the bus
(depending upon spacing) will lower the total load to about
27 Ohms (54 Ohm bus). The Serializer is designed for DC
loads between 27 and 100 Ohms.
The Serializer and Deserializer can also be used in
point-to-point configuration of a backplane, PCB trace or
through a twisted pair cable. In point-to-point configurations
the transmission media need only be terminated at the re-
ceiver end. In the point-to-point configuration the potential of
offsetting the ground levels of the Serializer vs. the Deserial-
izer must be considered. Bus LVDS provides a plus / minus
one volt common mode range at the receiver inputs.
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