CY24239 Cypress Semiconductor, CY24239 Datasheet - Page 3

• Manufacturer Part Number: CY24239
• Description: Spread Spectrum Frequency Timing Generator
• Manufacturer: Cypress Semiconductor

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Functional Description
I/O Pin Operation
Pins 2, 8, 9, 29, and 30 are dual-purpose l/O pins. Upon power-
up these pins act as logic inputs, allowing the determination of
assigned device functions. A short time after power-up, the
logic state of each pin is latched and the pins become clock
outputs. This feature reduces device pin count by combining
clock outputs with input select pins.
An external 10-k
the l/O pin and ground or V
latch to “0,” connection to V
Figure 2 show two suggested methods for strapping resistor
connections.
Upon CY24239 power-up, the first 2 ms of operation is used
for input logic selection. During this period, the five I/O pins (2,
8, 9, 29, 30) are three-stated, allowing the output strapping
resistor on the l/O pins to pull the pins and their associated
capacitive clock load to either a logic HIGH or LOW state. At
the end of the 2-ms period, the established logic “0” or “1”
Document #: 38-07038 Rev. **
Power-on
Reset
Timer
Power-on
Reset
Timer
CY24239
CY24239
“strapping” resistor is connected between
DD
DD
Figure 1. Input Logic Selection Through Resistor Load Option
sets a latch to “1.” Figure 1 and
. Connection to ground sets a
Output Three-state
Output Three-state
Figure 2. Input Logic Selection Through Jumper Option
Output
Buffer
Output
Buffer
Q
Q
Latch
Latch
Data
Data
D
D
Hold
Output
Low
Hold
Output
Low
(Load Option 1)
(Load Option 0)
condition of the l/O pin is latched. Next the output buffer is
enabled, converting the l/O pins into operating clock outputs.
The 2-ms timer starts when V
can only be reset by turning V
It should be noted that the strapping resistors have no signifi-
cant effect on clock output signal integrity. The drive imped-
ance of clock output (<40 , nominal), which is minimally af-
fected by the 10-k strap to ground or V
termination resistor, the output strapping resistor should be
placed as close to the l/O pin as possible in order to keep the
interconnecting trace short. The trace from the resistor to
ground or V
prevent system noise coupling during input logic sampling.
When the clock outputs are enabled following the 2-ms input
period, the specified output frequency is delivered on the pin,
assuming that V
full value, output frequency initially may be below target but will
increase to target once V
case, a short output clock cycle may be produced from the
CPU clock outputs when the outputs are enabled.
10 k
Jumper Options
10 k
10 k
V
DD
DD
should be kept less than two inches in length to
DD
V
Resistor Value R
DD
has stabilized. If V
R
R
Output Strapping Resistor
Output Strapping Resistor
DD
Series Termination Resistor
Series Termination Resistor
voltage has stabilized. In either
DD
DD
reaches 2.0V. The input bits
off and then back on again.
Clock Load
Clock Load
DD
DD
has not yet reached
. As with the series
CY24239
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