CY24239 Cypress Semiconductor, CY24239 Datasheet - Page 5

• Manufacturer Part Number: CY24239
• Description: Spread Spectrum Frequency Timing Generator
• Manufacturer: Cypress Semiconductor

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Serial Data Interface
The CY24239 features a two-pin, serial data interface that can
be used to configure internal register settings that control par-
ticular device functions. Upon power-up, the CY24239 initial-
izes with default register settings, therefore the use of this se-
rial data interface is optional. The serial interface is write-only
(to the clock chip) and is the dedicated function of device pins
SDATA and SCLOCK. In motherboard applications, SDATA
and SCLOCK are typically driven by two logic outputs of the
Table 3. Serial Data Interface Control Functions Summary
Table 4. Byte Writing Sequence
Document #: 38-07038 Rev. **
Output Disable
CPU Clock Frequency
Selection
Spread Spectrum
Enabling
Output Three-state
Test Mode
(Reserved)
Byte Sequence
Control Function
10
11
1
2
3
4
5
6
7
8
9
Slave Address
Command
Code
Byte Count
Data Byte 0
Data Byte 1
Data Byte 2
Data Byte 3
Data Byte 4
Data Byte 5
Data Byte 6
Data Byte 7
Byte Name
Any individual clock output(s) can be disabled. Dis-
abled outputs are actively held low.
Provides CPU/PCI frequency selections alternate
to the selections that are provided by the FS0:3
pins. Frequency is changed in a smooth and con-
trolled fashion.
Enables or disables spread spectrum clocking.
Puts all clock outputs into a high-impedance state. Production PCB testing.
All clock outputs toggle in relation to X1 input, inter-
nal PLL is bypassed. Refer to Table 5.
Reserved function for future device revision or pro-
duction device testing.
11010010
Don’t Care
Don’t Care
Refer to Table 5 The data bits in Data Bytes 0–7 set internal CY24239 registers that
Don’t Care
Bit Sequence
Description
Commands the CY24239 to accept the bits in Data Bytes 0–7 for internal
register configuration. Since other devices may exist on the same com-
mon serial data bus, it is necessary to have a specific slave address for
each potential receiver. The slave receiver address for the CY24239 is
11010010. Register setting will not be made if the Slave Address is not
correct (or is for an alternate slave receiver).
Unused by the CY24239, therefore bit values are ignored (“Don’t Care”).
This byte must be included in the data write sequence to maintain proper
byte allocation. The Command Code Byte is part of the standard serial
communication protocol and may be used when writing to another ad-
dressed slave receiver on the serial data bus.
Unused by the CY24239, therefore bit values are ignored (“Don’t Care”).
This byte must be included in the data write sequence to maintain proper
byte allocation. The Byte Count Byte is part of the standard serial com-
munication protocol and may be used when writing to another ad-
dressed slave receiver on the serial data bus.
control device operation. The data bits are only accepted when the Ad-
dress Byte bit sequence is 11010010, as noted above. For description
of bit control functions, refer to Table 5, Data Byte Serial Configuration
Map.
Unused by the CY24239, therefore bit values are ignored (“don’t care”).
chipset. Clock device register changes are normally made
upon system initialization, if any are required. The interface
can also be used during system operation for power manage-
ment functions. Table 3 summarizes the control functions of
the serial data interface.
Operation
Data is written to the CY24239 in eleven bytes of eight bits
each. Bytes are written in the order shown in Table 4.
Unused outputs are disabled to reduce EMI
and system power. Examples are clock out-
puts to unused PCI slots.
For alternate microprocessors and power
management options. Smooth frequency tran-
sition allows CPU frequency change under
normal system operation.
For EMI reduction.
Production PCB testing.
No user application. Register bit must be writ-
ten as 0.
Byte Description
Common Application
CY24239
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