CY28347 Cypress Semiconductor, CY28347 Datasheet
CY28347
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CY28347 Summary of contents
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... VSSD 18 39 VSS48M 19 38 DDRT2 **FS3/48M 20 37 DDRC2 **FS2/24_48M 21 36 DDRT3 VDD48M 35 22 DDRC3 VDD VDDD 23 34 VSS 24 33 VSSD 25 32 IREF DDRT4 *PD DDRC4 30 SCLK 27 DDRT5 SDATA 29 28 DDRC5 , • San Jose CA 95134 • 408-943-2600 Revised December 26, 2002 CY28347 PCI 33.40 33.40 30.00 33.33 36.00 35.00 32.00 35.00 38.50 36.67 30.00 30.00 30.00 33.33 33.33 33.33 ...
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... USB clock output. O PCI Clock Output. Power-on Bidirectional Input/Output. At power-up, FS2 is the input. When the PD power supply voltage crosses the input threshold voltage, FS2 state is latched and this pin becomes 24_48M, a SIO programmable clock output. (range 200 k to 500 k ). CY28347 Description Page ...
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... Ground for DDR clocks. Ground for 48M clock. Ground for CPUCS_T/C clocks. Common ground. Pin 26 Pin 18 CPU_STP# Reserved Reference R, IREF = VDD/(3*Rr 221 1%, IREF = 5. 475 1%, IREF = 2.32 mA CY28347 Description . See Table 2. SS Pin 8 PCI_STP# Reserved Output Current VOH@Z IOH = 4* Iref 1.0V@50 IOH = 6* Iref 0.7V@50 Page ...
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... Byte count from slave - 8 bits 38 Acknowledge 39:46 Data byte from slave - 8 bits 47 Acknowledge 48:55 Data byte from slave - 8 bits 56 Acknowledge .... Data bytes from slave/Acknowledge .... Data byte N from slave - 8 bits .... Not Acknowledge .... Stop Byte Read Protocol Bit Description 1 Start 2:8 Slave address - 7 bits 9 Write CY28347 Page ...
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... PCI clock output drive strength 0 = Normal increase the drive strength 20%. PCI_F 1 = output enabled (running output disabled asynchronously in a LOW state. Reserved, set = 1. CY28347 Acknowledge from slave Command Code - 8 bits “1xxxxxxx” stands for byte operation bit[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave ...
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... LOW state. REF1 1 = output enabled (running output disabled asynchro- nously in a LOW state. (K7 Mode only.) REF0 1 = strength strength x 2 REF1 1 = strength strength x 2 (K7 Mode only) AGP(0:2) Skew Shift CY28347 Description Description Description Default –280 ps +280 ps +480 ps Page ...
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... CPU frequency at very high resolution (accuracy). All other synchronous clocks (clocks that are generated from the same PLL, such as PCI) remain at their existing ratios relative to the CPU clock. CU/AGP Ratio Frequency Selection Default 2/1 2.5/1 3/1 Description Description Description CY28347 Page ...
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... R and N register mux selection. 0=R and N values come from the ROM. 1=data is load from DAF (I2C) registers. Spread Spectrum Clock Generation (SSCG) Spread Spectrum is enabled/disabled via SMBus register Byte 1, Bit 6. Table 9. Spread Spectrum Table Mode P 0 96016000 CY28347 Description Description SST1 SST0 % Spread 0 0 –1. –1. –0. – ...
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... MHz Min. Max. Min. Max 69.84 71.0 69.84 71.0 0.7V V 0. 0. 10.0 10.0 500 500 30 30 CY28347 and V should be constrained to the IN OUT < OUT 2.5 ± 5 °C to +70 °C) DDI DD A Min. Typ. 2.0 2.2 0 [4] 156 [4] 177 3 ...
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... Vp+.6V .4 Vp+.6V .4 500 1100 500 1100 500 15.5 10.0 10.5 7.35 CY28347 133 MHz 200 MHz Max. Min. Max. Unit 5,6,10,14,15 7.65 4.85 5.1 ns 5,6,10,14,15 700 175 700 ps 15,16 20% 20% 16,17 125 125 ps 10,15,16,18 100 100 ps 10,11,12,14,1 5 150 150 ps 6,10,11,12,14, 15 430 280 430 mV 15 ...
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... CY28347 133 MHz 200 MHz Max. Min. Max. Unit 0.4 1.6 0.4 1.6 ns 5,10,21 0.4 Vp+ 0.4 Vp 0.6V 0.6V 0.5*VD 0.5*VD 0.5* DI+0.2 DI–0.2 DI+0 ...
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... T PCB 100 T PCB Figure 1. Differential DDR Termination CY28347 133 MHz 200 MHz Max. Min. Max. Unit 5,10,6 71.0 69.8413 71.0 ns 5,6,10 1.0 4.0 1.0 4.0 ns 10,21 1000 1000 ps 6,10,11,12 0.5*VD 0.5*VD 0.5* DD+0.2 DD–0.2 DD+0.2 0.7 VDDD + 0.7 VDDD + ...
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... Ohm 500 Ohm 3.3V Figure 2. K7 Termination 6” 6” Figure 3. Chipset Termination amplitude signalling and Figure 5 is for the 0.7V amplitude signalling. T 33.2 PCB 475 T 33.2 PCB 63.4 63.4 Figure 4. P4 1.0V Configuration CY28347 Measurement Point 20 pF Measurement Point 20 pF Measurement Point 2 pF Measurement Point 2 pF Page ...
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... PCB 49.9 Figure 5. P4 0.7V Configuration Offset (ps) Tolerance (ps) 750 500 Clock Name CSAGP t AP Figure 6. Clock Timing Relationships CY28347 Measurem ent Point 2 pF Measurem ent Point 2 pF Conditions 500 CPUCS Leads 500 AGP Leads Max. Load (in pF See Figure 1 See Figure 4 and Figure 5 ...
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... Synchronous manner meaning that no Float short or stretched clock pulses will be produce when the clock resumes. The maximum latency from the deassertion to active outputs is no more than two CPU clock cycles. CY28347 Page ...
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... Document #: 38-07352 Rev. *C The final state of the stopped CPU signal is CPUOD_T = LOW and CPUOD_C = LOW. short or stretched clock pulses will be produce when the clock resumes. The maximum latency from the deassertion to active outputs is no more than two CPU clock cycles. CY28347 Page ...
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... Figure 12. PCI_STP# Deassertion Waveform Power Down Assertion (P4 Mode) When PD# is sampled LOW by two consecutive rising edges of CPUC clock then all clocks must be held LOW on their next HIGH to LOW transition. CPUT clocks must be held with a value Iref, CY28347 ). The setup Page ...
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... 133M 133M 33M 66M 48M 14.318M 133M 133M H z Figure 14. Power-down Deassertion Timing Waveform (in P4 Mode) Document #: 38-07352 Rev. *C <1.5 m sec CY28347 Page ...
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... LOW state (see Figure 15 below), all PLLs are shut off, and the crystal oscillator is disabled. When the device is shutdown, the I2C function is also disabled. order to guarantee a glitch-free operation, no partial clock pulses. <1.5 msec CY28347 Page ...
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... VTT_GD# State 1 State Package Type CY28347 State 3 (Note A) On [26 tio n ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 56-lead Shrunk Small Outline Package O56 CY28347 51-85062-*C 51-85060-*B ...
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... Document Title: CY28347 Universal Single-chip Clock Solution for VIA P4M266/KM266 DDR Systems Document Number: 38-07352 Issue REV. ECN NO. Date ** 112259 03/29/02 *A 120421 10/23/02 *B 121771 12/06/02 *C 122902 12/26/02 Document #: 38-07352 Rev. *C Orig. of Change Description of Change DMG New Data Sheet RGL Changed the package drawing and dimension per Cypress standards. ...