CY28347 Cypress Semiconductor, CY28347 Datasheet - Page 2

• Manufacturer Part Number: CY28347
• Description: Universal Single-chip Clock Solution
• Manufacturer: Cypress Semiconductor

Document #: 38-07352 Rev. *C
Pin Description
3
4
1
56
44,42,38,
36,32,30
43,41,37
35,31,29
7
12
53
52
14,15,17
48,49
18
10
20
11
21
Note:
2.
Pin
PU = internal pull-up. PD = internal pull-down. Typically = 250 k
XIN
XOUT
FS0/REF0
VTTPWRGD#
REF1
DDRT(0:5)
DDRC(0:5)
SELP4_K7#/
AGP1
MULTSEL/PCI2 VDDPCI
CPUT/CPUOD_T
CPUC/CPUOD_C
PCI (3:5)
CPUCS_T/C
CPU_STP#
FS1/PCI_F
FS3/48M
PCI1
FS2/24_48M
Name
[2]
VDDAGP I/O
VDD48M I/O
VDD48M I/O
VDDPCI
VDDPCI
VDDPCI
VDDPCI
VDDR
VDDR
VDDD
VDDD
VDDC
VDDC
VDDI
PWR
VDD
VDD
I/O
I/O
PU
PU
I/O
PU
PU
I/O
PD
PD
PD
O
O
O
O
O
O
O
O
O
I
I
I
Oscillator Buffer Input. Connect to a crystal or to an external clock.
Oscillator Buffer Output. Connect to a crystal. Do not connect when an external
clock is applied at XIN.
Power-on Bidirectional Input/Output. At power-up, FS0 is the input. When the
power supply voltage crosses the input threshold voltage, FS0 state is latched and
this pin becomes REF0, buffered copy of signal applied at XIN. (1–2 x strength,
selectable by SMBus. Default value is 1 x strength.)
If SELP4_K7# = 1, with a P4 processor setup as CPU(T:C). At power-up,
VTT_PWRGD# is an input. When this input is sampled LOW, the FS (3:0) and
MULTSEL are latched and all output clocks are enabled. After the first transition to
a LOW on VTT_PWRGD#, this pin is ignored and will not effect the behavior of the
device thereafter. When the VTT_PWRGD# feature is not used, please connect this
signal to ground through a 10K resistor.
If SELP4_K7# = 0, with an Athlon (K7) processor as CPUOD_(T:C).
VTT_PWRGD# function is disabled, and the feature is ignored. This pin becomes
REF1 and is a buffered copy of the signal applied at XIN.
These pins are configured for DDR clock outputs. They are “True” copies of
signal applied at Pin45, BUF_IN.
These pins are configured for DDR clock outputs. They are “Complementary”
copies of signal applied at Pin45, BUF_IN.
Power-on Bidirectional Input/Output. At power-up, SELP4_K7# is the input.
When the power supply voltage crosses the input threshold voltage, SELP4_K7#
state is latched and this pin becomes AGP1 clock output. SELP4_K7# = 1 selects
P4 mode. SELP4_K7# = 0 selects K7 mode.
Power-on Bidirectional Input/Output. At power-up, MULTSEL is the input. When
the power supply voltage crosses the input threshold voltage, MULTSEL state is
latched and this pin becomes PCI2 clock output. MULTSEL = 0, Ioh is 4 x
IREFMULTSEL = 1, Ioh is 6 x IREF
3.3V True CPU Clock Outputs. This pin is programmable through strapping pin7,
SELP4_K7#. If SELP4_K7# = 1, this pin is configured as the CPUT Clock Output.
If SELP4_K7# = 0, this pin is configured as the CPUOD_T Open Drain Clock Output.
See Table 1.
3.3V Complementary CPU Clock Outputs. This pin is programmable through
strapping pin7, SELP4_K7#. If SELP4_K7# = 1, this pin is configured as the CPUC
Clock Output. If SELP4_K7# = 0, this pin is configured as the CPUOD_C Open
Drain Clock Output. See Table 1.
PCI Clock Outputs. Are synchronous to CPU clocks. See Table 1.
2.5V CPU Clock Outputs for Chipset. See Table 1.
If pin 6 is pulled down at power on reset, then this pin becomes CPU_STP#. When
CPU_STP# is asserted LOW, then both of the CPU signals stop at the next HIGH
to LOW transition or stays LOW if it already is LOW. This does not stop the CPUCS
signals.
Power-on Bidirectional Input/Output. At power-up, FS1 is the input. When the
power supply voltage crosses the input threshold voltage, FS1 state is latched and
this pin becomes PCI_F clock output.
Power-on Bidirectional Input/Output. At power-up, FS3 is the input. When the
power supply voltage crosses the input threshold voltage, FS3 state is latched and
this pin becomes 48M, a USB clock output.
PCI Clock Output.
Power-on Bidirectional Input/Output. At power-up, FS2 is the input. When the
power supply voltage crosses the input threshold voltage, FS2 state is latched and
this pin becomes 24_48M, a SIO programmable clock output.
(range 200 k to 500 k ).
Description
CY28347
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