CY28347 Cypress Semiconductor, CY28347 Datasheet - Page 16

• Manufacturer Part Number: CY28347
• Description: Universal Single-chip Clock Solution
• Manufacturer: Cypress Semiconductor

Document #: 38-07352 Rev. *C
CPU_STP# Assertion (K7 Mode)
When CPU_STP# pin is asserted, all CPU outputs will be
stopped after being sampled by two rising CPUC clock edges.
CPU_STP# Deassertion (K7 Mode)
The deassertion of the CPU_STP# signal will cause all CPU
outputs that were stopped to resume normal operation in a
synchronous manner. Synchronous manner meaning that no
CPU_STP#
CPUOD_C
CPUOD_T
CPUCS_C
CPU_STP#
CPUCS_T
CPUOD_C
CPUOD_T
Figure 10. CPU_STP# Deassertion Waveform (K7 Mode)
Figure 9. CPU_STP# Assertion Waveform (K7 Mode)
The final state of the stopped CPU signal is CPUOD_T = LOW
and CPUOD_C = LOW.
short or stretched clock pulses will be produce when the clock
resumes. The maximum latency from the deassertion to active
outputs is no more than two CPU clock cycles.
CY28347
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