AN2184 Freescale Semiconductor / Motorola, AN2184 Datasheet - Page 10

• Manufacturer Part Number: AN2184
• Description: MCF5272 Interrupt Service Routine for the Physical Layer Interface Controller
• Manufacturer: Freescale Semiconductor / Motorola

Part V Periodic Interrupt Process
This document does not intend to define all the meanings of the P n PSR register. For more information, the
user should read the MCF5272 User’s Manual . This P n PSR register is involved in the data processing. All
P n RB x and P n TB x registers, either in IDL or GCI modes of operation, will use these registers. There is no
difference between those two modes as far as they are concerned. P n PSR register is updated every 500µs.
As long as the interrupt enable (IE) bits are set to invoke the interrupt service routine, the B xRDF bits will
be set every 500µs, and a register access will be achieved to clear this interrupt.
This section is explained in two parts:
5.1 ISR Bubble Definitions
To assure that the following flow charts are well understood, this section defines the bubble shapes used in
the illustrations:
Periodic Interrupt Process ISR Bubble Definitions
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One port only is enabled: description of how to handle all the bits involved in PnPSR
Multiple ports are enabled: description of how to access the ports that created this interrupt
Start or End of the process
Test Condition
Bits
7–5
3–0
4
Start
C3–C0 C/I bits. The CPU writes C/I data to be transmitted, on the GCI or SCIT channel 0,
Name
—
R
Reserved, should be cleared.
Ready. This bit is set by the CPU to indicate to the C/I channel controller that data is
ready for transmission. Setting this bit starts the C/I state machine, which responds
with the transmit acknowledge (ACK bit in the PnGCITS register) once transmission
of two successive C/I words is complete. This bit is automatically cleared by the GCI
controller when it generates an ACK. The clearing of this bit by reading this register
also clears the aperiodic GCT interrupt.
into these positions. The CPU must ensure that this data is not overwritten before it
has been transmitted the required minimum number of times, that is, before a
change is detected and confirmed by a receiver. A maskable interrupt is generated
when this data has been successfully transmitted.
Reset
Read
Field
Freescale Semiconductor, Inc.
Table 4. PnGCIT Register Field Descriptions
For More Information On This Product,
7
MCF5272 Interrupt Service Routine
—
Figure 8. PnGCIT Register
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5
0000_0000
F
4
R/W
Description
C3
3
C2
2
C1
1
C0
0