AN2184 Freescale Semiconductor / Motorola, AN2184 Datasheet - Page 31

• Manufacturer Part Number: AN2184
• Description: MCF5272 Interrupt Service Routine for the Physical Layer Interface Controller
• Manufacturer: Freescale Semiconductor / Motorola

P2B2RR
P3B2RR
P0DRR
P1DRR
P2DRR
P3DRR
P0B1TR
P1B1TR
P2B1TR
P3B1TR
P0B2TR
P1B2TR
P2B2TR
P3B2TR
P0DTR
P1DTR
P2DTR
P3DTR
PLCR0
PLCR1
PLCR2
PLCR3
P0ICR
P1ICR
P2ICR
P3ICR
P0GMR
P1GMR
P2GMR
P3GMR
P0GMT
P1GMT
P2GMT
P3GMT
PGMTS
PGMTA
P0GCIR
P1GCIR
P2GCIR
P3GCIR
P0GCIT
P1GCIT
P2GCIT
P3GCIT
PGCITSR
PDCSR
P0PSR
P1PSR
P2PSR
P3PSR
PASR
PLCR
PDRQR
P0SDR
P1SDR
P2SDR
P3SDR
PCSR
Shown below are the interrupt vector file. As long as the purpose of this evaluation is PLIC oriented, not all
vectors need to correspond to a real ISR address:
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
PLIC_Reg_Offset+$18
PLIC_Reg_Offset+$1C
PLIC_Reg_Offset+$20
PLIC_Reg_Offset+$21
PLIC_Reg_Offset+$22
PLIC_Reg_Offset+$23
PLIC_Reg_Offset+$28
PLIC_Reg_Offset+$2C
PLIC_Reg_Offset+$30
PLIC_Reg_Offset+$34
PLIC_Reg_Offset+$38
PLIC_Reg_Offset+$3C
PLIC_Reg_Offset+$40
PLIC_Reg_Offset+$44
PLIC_Reg_Offset+$48
PLIC_Reg_Offset+$49
PLIC_Reg_Offset+$4A
PLIC_Reg_Offset+$4B
PLIC_Reg_Offset+$50
PLIC_Reg_Offset+$52
PLIC_Reg_Offset+$54
PLIC_Reg_Offset+$56
PLIC_Reg_Offset+$58
PLIC_Reg_Offset+$5A
PLIC_Reg_Offset+$5C
PLIC_Reg_Offset+$5E
PLIC_Reg_Offset+$60
PLIC_Reg_Offset+$62
PLIC_Reg_Offset+$64
PLIC_Reg_Offset+$66
PLIC_Reg_Offset+$68
PLIC_Reg_Offset+$6A
PLIC_Reg_Offset+$6C
PLIC_Reg_Offset+$6E
PLIC_Reg_Offset+$71
PLIC_Reg_Offset+$72
PLIC_Reg_Offset+$74
PLIC_Reg_Offset+$75
PLIC_Reg_Offset+$76
PLIC_Reg_Offset+$77
PLIC_Reg_Offset+$78
PLIC_Reg_Offset+$79
PLIC_Reg_Offset+$7A
PLIC_Reg_Offset+$7B
PLIC_Reg_Offset+$7F
PLIC_Reg_Offset+$83
PLIC_Reg_Offset+$84
PLIC_Reg_Offset+$86
PLIC_Reg_Offset+$88
PLIC_Reg_Offset+$8A
PLIC_Reg_Offset+$8C
PLIC_Reg_Offset+$8F
PLIC_Reg_Offset+$92
PLIC_Reg_Offset+$94
PLIC_Reg_Offset+$96
PLIC_Reg_Offset+$98
PLIC_Reg_Offset+$9A
PLIC_Reg_Offset+$9E
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;B2 Data Receive, Port2
;B2 Data Receive, Port3
;D Data Receive, Port0
;D Data Receive, Port1
;D Data Receive, Port2
;D Data Receive, Port3
;B1 Data Transmit, Port0
;B1 Data Transmit, Port1
;B1 Data Transmit,Port2
;B1 Data Transmit, Port3
;B2 Data Transmit, Port0
;B2 Data Transmit, Port1
;B2 Data Transmit, Port2
;B2 Data Transmit, Port3
;D Data Transmit, Port0
;D Data Transmit, Port1
;D Data Transmit, Port2
;D Data Transmit, Port3
;GCI/IDL config, Port0
;GCI/IDL config, Port1
;GCI/IDL config, Port2
;GCI/IDL config, Port3
;GCI Int config, Port0
;GCI Int config, Port1
;GCI Int config, Port2
;GCI Int config, Port3
;GCI Monitor RX, Port0
;GCI Monitor RX, Port1
;GCI Monitor RX, Port2
;GCI Monitor RX, Port3
;GCI Monitor TX, Port0
;GCI Monitor TX, Port1
;GCI Monitor TX, Port2
;GCI Monitor TX, Port3
;GCI Monitor TX status
;GCI Monitor TX abort
;GCI C/I RX, Port0
;GCI C/I RX, Port1
;GCI C/I RX, Port2
;GCI C/I RX, Port3
;GCI C/I TX, Port0
;GCI C/I TX, Port1
;GCI C/I TX, Port2
;GCI C/I TX, Port3
;GCI C/I TX status
;D Channel Status
;Port Status, Port0
;Port Status, Port1
;Port Status, Port2
;Port Status, Port3
;Aperiodic Status Reg
;Loopback Control
;D Channel Request
;Sync Delay, Port0
;Sync Delay, Port1
;Sync Delay, Port2
;Sync Delay, Port3
;Clock Select
Appendix A Software Configuration
31