CY28RS480-1 Cypress Semiconductor, CY28RS480-1 Datasheet - Page 7

• Manufacturer Part Number: CY28RS480-1
• Description: Clock Generator
• Manufacturer: Cypress Semiconductor

Document #: 38-07714 Rev. *C
Table 4. Crystal Recommendations
Crystal Recommendations
The CY28RS480-1 requires a parallel resonance crystal.
Substituting a series resonance crystal will cause the
CY28RS480-1 to operate at the wrong frequency and violate
the ppm specification. For most applications there is a
300-ppm frequency shift between series and parallel crystals
due to incorrect loading.
Crystal Loading
Crystal loading plays a critical role in achieving low ppm perfor-
mance. To realize low ppm performance, the total capacitance
the crystal will see must be considered to calculate the appro-
priate capacitive loading (CL).
The following diagram shows a typical crystal configuration
using the two trim capacitors. An important clarification for the
following discussion is that the trim capacitors are in series
with the crystal not parallel. It’s a common misconception that
load capacitors are in parallel with the crystal and should be
approximately equal to the load capacitance of the crystal.
This is not true.
Calculating Load Capacitors
In addition to the standard external trim capacitors, trace
capacitance and pin capacitance must also be considered to
correctly calculate crystal loading. As mentioned previously,
the capacitance on each side of the crystal is in series with the
crystal. This means the total capacitance on each side of the
crystal must be twice the specified crystal load capacitance
(CL). While the capacitance on each side of the crystal is in
series with the crystal, trim capacitors (Ce1,Ce2) should be
calculated to provide equal capacitive loading on both sides.
As mentioned previously, the capacitance on each side of the
crystal is in series with the crystal. This mean the total capac-
itance on each side of the crystal must be twice the specified
load capacitance (CL). While the capacitance on each side of
the crystal is in series with the crystal, trim capacitors
14.31818 MHz
Frequency
(Fund)
Figure 1. Crystal Capacitive Clarification
Cut
AT
Loading Load Cap
Parallel
20 pF
PRELIMINARY
0.1 mW
(max.)
Drive
Shunt Cap
www.DataSheet.co.kr
(Ce1,Ce2) should be calculated to provide equal capacitance
loading on both sides.
Use the following formulas to calculate the trim capacitor
values for Ce1 and Ce2.
CL ....................................................Crystal load capacitance
CLe ......................................... Actual loading seen by crystal
using standard value trim capacitors
Ce ..................................................... External trim capacitors
Cs ..............................................Stray capacitance (terraced)
Ci .......................................................... Internal capacitance
(lead frame, bond wires etc.)
CLK_REQ[0:1]# Description
The CLKREQ#[1:0] signals are active LOW input used for
clean stopping and starting selected SRC outputs. The outputs
controlled by CLKREQ#[1:0] are determined by the settings in
register bytes 3 and 4. The CLKREQ# signal is a debounced
signal in that it’s state must remain unchanged during two
consecutive rising edges of DIFC to be recognized as a valid
assertion or deassertion. (The assertion and deassertion of
this signal is absolutely asynchronous.)
(max.)
5 pF
CLe
Cs1
Total Capacitance (as seen by the crystal)
=
Motional
0.016 pF
Figure 2. Crystal Loading Example
(max.)
Ce1
(
Load Capacitance (each side)
Ce1 + Cs1 + Ci1
X1
Ci1
Ce = 2 * CL – (Cs + Ci)
Clock Chip
1
XTAL
Tolerance
35 ppm
(max.)
Ci2
+
X2
1
Ce2
Ce2 + Cs2 + Ci2
CY28RS480-1
Stability
30 ppm
(max.)
Cs2
1
3 to 6p
33pF
Pin
Trim
Page 7 of 16
Trace
2.8pF
(max.)
Aging
5 ppm
)
Datasheet pdf - http://www.DataSheet4U.net/