CY28RS480-1 Cypress Semiconductor, CY28RS480-1 Datasheet - Page 9

• Manufacturer Part Number: CY28RS480-1
• Description: Clock Generator
• Manufacturer: Cypress Semiconductor

Document #: 38-07714 Rev. *C
CLK_STOP
When CLK_STOP is sampled HIGH by two consecutive rising
edges of CPUC, all single-ended outputs must be held LOW
on their next HIGH-to-LOW transition and differential clocks
must held LOW on the next diff clock# HIGH-to-LOW
transition. This diagram and description is applicable to valid
CPU frequencies
.
CPUC, 133MHz
CPUC, 133MHz
CPUT, 133MHz
CPUT, 133MHz
SRCC 100MHz
SRCC 100MHz
SRCT 100MHz
SRCT 100MHz
CPU_CLOCK
PCI, 33 MHz
USB, 48MHz
PCI, 33MHz
USB, 48MHz
CLK_STOP
REF
REF
Figure 5. CLK_STOP Deassertion Timing Waveform
Figure 4. CLK_STOP Assertion Timing Waveform
PRELIMINARY
Tdrive_PWRDN#
<300µS, >200mV
REFCLK
Tstable
< 2
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