CY28RS480-1 Cypress Semiconductor, CY28RS480-1 Datasheet - Page 8

• Manufacturer Part Number: CY28RS480-1
• Description: Clock Generator
• Manufacturer: Cypress Semiconductor

Document #: 38-07714 Rev. *C
CLK_REQ[0:1]# Assertion
The impact of asserting the CLKREQ#[1:0] pins is all DIF
outputs that are set in the control registers to stoppable via
assertion of CLKREQ#[1:0] are to be stopped after their next
transition. When the control register CLKREQ# drive mode bit
is programmed to ‘0’, the final state of all stopped SRC signals
is SRCT clock = HIGH and SRCC = LOW. There is to be no
change to the output drive current values, SRCT will be driven
high with a current value equal 6 x Iref,. When the control
register CLKREQ# drive mode bit is programmed to ‘1’, the
final state of all stopped DIF signals is LOW, both SRCT clock
and SRCC clock outputs will not be driven.
SRCC(free running)
SRCT(free running)
SRCT(stoppable)
SRCT(stoppable)
CLKREQ#X
Figure 3. CLK_REQ#[0:1] Assertion/Deassertion Waveform
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CLK_REQ[0:1]# Deassertion
All differential outputs that were stopped are to resume normal
operation in a glitch free manner. The maximum latency from
the de-assertion to active outputs is between 2-6 SRC clock
periods (2 clocks are shown) with all SRC outputs resuming
simultaneously. If the CLKREQ# drive mode bit is
programmed to ‘1’ three-state), the all stopped SRC outputs
must be driven high within 10 ns of CLKREQ#[1:0] deassertion
to a voltage greater than 200 mV.
CY28RS480-1
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