AN2692 Freescale Semiconductor / Motorola, AN2692 Datasheet
AN2692
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AN2692 Summary of contents
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... Internet. EMBEDDED DEVICE MOTOR This product incorporates SuperFlash technology licensed from SST. © Freescale Semiconductor, Inc., 2004. All rights reserved. INTERNET CONTROL BOARD Figure 1. Embedded Device on Internet AN2692 Rev. 0.2, 9/2004 Figure 1 shows a simplified REMOTE HOST ...
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Introduction The MC9S12NE64 is a 16-bit MCU based on Freescale Semiconductor’s HCS12 CPU platform the first in a series of low-cost Ethernet-capable MCUs in a small package. The MC9S12NE64 provides a complete, integrated, single-chip Ethernet solution. This application ...
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Ethernet packet destination hardware address. Depending on the destination hardware address of the incoming packet, the device will either ignore the message or accept it for further processing. MAC HEADER ENCAPSULATED DATA (LAYER 3 AND UP) MAC ...
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Introduction • Encapsulated data portion — 1500 bytes of user data. • Frame check sequence trailer (frame check sequence) — 4-byte value that contains a 32-bit cyclic redundancy check (CRC) value. Ethernet is not the only component of ...
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MC9S12NE64 Integrated Ethernet Controller This section will introduce the MC9S12NE64 and provide an overview of the MC9S12NE64 integrated Ethernet controller. The discussion will also include a summary of the minimum number of printed circuit board (PCB) components required in an ...
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MC9S12NE64 Integrated Ethernet Controller 2 X SCI SPI VREG 3 2.5 V CONVERTER 18 KEY WAKEUP IRQ PORTS Figure 4. Block Diagram of the MC9S12NE64 MC9S12NE64 System Overview The MC9S12NE64 is a single-chip Ethernet solution. Having an on-chip ...
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To configure the bus clock to 25 MHz with a 25-MHz clock input, the CRG (clock and reset generator) must be configured so that the PLL setting yields the 25-MHz internal bus clock setting. See the section for details. C1 ...
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MC9S12NE64 Integrated Ethernet Controller MII_TXER/KWH6/PH6 1 MII_TXEN/KWH5/PH5 2 MII_TXCLK/KWH4/PH4 3 MII_TXD3/KWH3/PH3 4 MII_TXD2/KWH2/PH2 5 MII_TXD1/KWH1/PH1 6 MII_TXD0/KWH0/PH0 7 MII_MDC/KWJ0/PJ0 8 MII_MDIO/KWJ1/PJ1 9 ADDR0/DATA0/PB0 10 ADDR1/DATA1/PB1 11 ADDR2/DATA2/PB2 12 ADDR3/DATA3/PB3 13 VDDX1 14 VSSX1 15 ADDR4/DATA4/PB4 16 ADDR5/DATA5/PB5 17 ADDR6/DATA6/PB6 18 ...
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Figure 7 illustrates the dependence of the peripherals, core, and memory on the CRG clock outputs, including the core, bus (IP ), and oscillator clocks. Bus EXTAL CRG The modules shown in Figure 7 clock signals from the CRG is ...
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MC9S12NE64 Integrated Ethernet Controller These registers can be used to configure the internal bus clock to 25 MHz, which is required by the MC9S12NE64 when operating at 100 Mbps. To configure the internal bus clock to 25 MHz with a ...
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The FLASH uses the PRDIV8 and FDIV[5:0] bits in the FCLKDIV register to divide the oscillator clock down to the required clock range. PRDIV8 is a 1-bit prescaler value that, if set, divides the oscillator clock PRDIV8 ...
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MC9S12NE64 Integrated Ethernet Controller IIC Clock The IIC bus is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange between two devices. The only clock source for the IIC module is the bus clock. The ...
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The ATD conversion clock frequency is a function of both the bus clock and an ATD prescaler value, PRS[4:0]. The ATD conversion clock frequency can be calculated using Equation 11. Equation 11: The PRS[4:0] bits are found in the ATD ...
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MC9S12NE64 and the IEEE 802.3 Standard MC9S12NE64 and the IEEE 802.3 Standard The MC9S12NE64 Ethernet controller is compliant with the IEEE 802.3 standard and the 802.3, 802.3u, and 802.3x specifications, so operation can be either 10 Mbps full-duplex, 10 Mbps ...
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MC9S12NE64 Ethernet Media Access Controller (EMAC) The EMAC is an implementation of a media access controller (MAC) as defined by the IEEE 802.3 Ethernet standard. The EMAC implements the data link layer as described in the communication model shown in ...
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MC9S12NE64 Ethernet Media Access Controller (EMAC) EMAC RX BUFFER A RAM INTERFACE INTERFACE SIGNALS RX BUFFER B INTERFACE MAC FLOW CONTROL RAM INTERFACE SIGNALS TX BUFFER INTERFACE IP BUS SIGNALS IP BUS REGISTER The following EMAC options are described in ...
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Bit 7 Read: EMACE Write: Reset: 0 Figure 10. Network Control (NETCTL) Register EMAC Enable (EMACE) Setting the EMAC enable (EMACE) bit in the NETCTL register enables the EMAC. Before enabling the EMAC important to configure several other ...
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MC9S12NE64 Ethernet Media Access Controller (EMAC) Table 1. MII Signal Descriptions (Continued) Hardware MAC Address Each network device should have a unique 6-byte media access control (MAC) hardware address that identifies that device on a network. A valid MAC hardware ...
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The MACAD registers are shown Read: Write: Reset Read: Write: Reset Read: Write: Reset MAC ...
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MC9S12NE64 Ethernet Media Access Controller (EMAC) Unicast Filter Mode In unicast filter mode, the EMAC uses the MAC unicast address (MACAD) registers, which contain the unique 6-byte address. The destination address of an incoming packet is compared to the MACAD ...
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Promiscuous Filter Mode Promiscuous filtering mode is set using the PROM of the RXCTS register. • PROM = 0 — Unicast, broadcast, and multicast filtering modes behave as described in the previous section • PROM = 1 — Promiscuous mode ...
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MC9S12NE64 Ethernet Media Access Controller (EMAC) MAC HEADER ENCAPSULATED DATA (LAYER 3 AND UP) MAC TRAILER Figure 15. Format and Content of Ethernet Packets (Repeated) Ethertype filtering allows only packets with an approved type/length field value to be accepted by ...
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Two receive buffers — Incoming Ethernet packets store the following data in a receive buffer if a buffer is available: – Destination address – Source address – Type/length – Data – Frame check sequence Each EMAC Ethernet buffer is ...
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MC9S12NE64 Ethernet Media Access Controller (EMAC) Because the maximum size of an Ethernet frame is approximately 1.5K, a setting of BUFMAP = 4 would allow each of the three MC9S12NE64 buffers to hold one Ethernet packet of the maximum allowable ...
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Hardware Generated Pause Control Frame Transmission If no transmission is in progress and the EMAC is in full-duplex mode, a PAUSE command can be launched by writing a value of 0x02 to the 2-bit transmit command (TCMD) field in the ...
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MC9S12NE64 Ethernet Media Access Controller (EMAC) The MDCSEL bit field sets the MDC frequency and must be equal-to or less-than 2.5 MHz, according to the IEEE 802.3 specification. Using the following equation, with a 25-MHz clock driving the MC9S12NE64, the ...
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MC9S12NE64 Ethernet Physical Transceiver (EPHY) The EPHY is an implementation of an Ethernet physical transceiver (PHY) as defined by IEEE 802.3 standard. For basic operation, the EPHY must be supplied a 25-MHz clock input specified at 25 ppm. The EPHY ...
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MC9S12NE64 Ethernet Physical Transceiver (EPHY) RxP 10BASE-T RECEIVER RxN 100BASE-TX RECEIVER 100BASE-TX LOOPBACK TxP 10BASET DRIVER TxN 100BASETX DRIVER R Bias VOLTAGE/CURRENT REFERENCES EPHY Registers and Configuration Options The integrated EPHY is designed to provide control and status access by ...
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Register Name Bit 7 Ethernet Physical Read: EPHYEN Transceiver Control Write: Register 0 Reset: 0 (EPHYCTL0) Ethernet Physical Read: 0 Transceiver Control Write: Register 1 Reset: 0 (EPHYCTL1) Figure 20. Ethernet Physical Transceiver Control Register 0 and Register 1 Before ...
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MC9S12NE64 Ethernet Physical Transceiver (EPHY) is not accessible from the MC9S12NE64 register map. With auto-negotiation disabled, the speed and duplex mode for the EPHY must be manually set using the MII management interface and writing to the DPLX and DATARATE ...
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PHY Control Register The PHY control register has several important control registers for EPHY basic operation. Some basic control settings are discussed in this section Read: LOOP DATA RESET ANE BACK RATE Write: Reset ...
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MC9S12NE64 Ethernet Physical Transceiver (EPHY Read: 0 LNK PDMD SPD Write: Reset Figure 24. Proprietary Status Register (MII Management Register 17) • ANCOMP and ANNC — Both indicate whether auto-negotiation is complete. ...
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Figure 25 shows the auto-negotiate advertisement register. Setting the bits for a particular Ethernet option ensures that a capability is advertised during auto-negotiation. For example, if the user does not want to allow a network device to ever negotiate to ...
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Initializing the MC9S12NE64 Ethernet Controller Initializing the MC9S12NE64 Ethernet Controller The EMAC and EPHY are designed as two separate modules on the MC9S12NE64, but if using the internal EPHY, they should be initialized together. The following procedure will prepare the ...
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Configure EPHY through the EMAC MII management interface — Configure speed, duplex mode, and flow control EPHY auto-negotiation advertisement by writing to the EPHY auto-negotiate advertisement register. 20. Configure EPHY through the EMAC MII management interface: a. Configure the ...
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Network Data Transaction at Upper Layer Protocols Network Data Transaction at Upper Layer Protocols Reception and transmission of Ethernet packets as described in the Interface section is not the level that typical user Ethernet applications use. Typically, a software stack ...
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... The Ethernet functionality of the MC9S12NE64 complies to the IEEE 802.3 specification to provide improved network functionality and interoperability. Configuration and initialization of this tightly-integrated solution is also enhanced by C-based development tools. Combining the MC9S12NE64 with a TCP/IP stack provides an interface for developing Ethernet-enabled embedded devices with a rich set of network functionality ...
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Notes Notes MC9S12NE64 Integrated Ethernet Controller, Rev. 0.2 38 This page is intentionally blank Freescale Semiconductor ...
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MC9S12NE64 Integrated Ethernet Controller, Rev. 0.2 Freescale Semiconductor This page is intentionally blank Notes 39 ...
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... Learn More: For more information about Freescale Semiconductor products, please visit http://www.freescale.com AN2692 Rev. 0.2, 9/2004 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document ...