AN2692 Freescale Semiconductor / Motorola, AN2692 Datasheet - Page 27

• Manufacturer Part Number: AN2692
• Description: MC9S12NE64 Integrated Ethernet Controller
• Manufacturer: Freescale Semiconductor / Motorola

MC9S12NE64 Ethernet Physical Transceiver (EPHY)
The EPHY is an implementation of an Ethernet physical transceiver (PHY) as defined by IEEE 802.3
standard. For basic operation, the EPHY must be supplied a 25-MHz clock input specified at 25 ppm.
The EPHY is compliant with IEEE 802.3 specifications for 10BASE-T (clause 14) and 100BASE-TX
(clauses 24 and 25).
The EPHY is also compliant with Ethernet operation using category 5 UTP copper cable at cable lengths
of 100 meters.
The EPHY (like the EMAC) supports the MII and the MII management interface
clause 22)
status. The EPHY also includes the following features:
The EPHY provides digital/analog encoding and decoding, which is required for the MC9S12NE64 to
communicate on the UTP cable. A block diagram of this peripheral is provided in the
shows that the clock input of the EPHY is the 25-MHz reference clock (REF CLOCK).
Freescale Semiconductor
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100BASE-TX
Technology
10BASE-T specification — PHY operation at 10 Mbps, called Ethernet, over un-shielded twisted
pair (UTP) copper cable.
100BASE-TX specification — PHY operation at 100 Mbps, called Fast Ethernet, also over UTP
copper cable.
Supports auto-negotiation
Auto-negotiation next page ability
Full-duplex and half-duplex support
Digital adaptive equalization
Baseline wander (BLW) correction
Loopback modes
10BASE-T
. The EMAC and EPHY use the MII to exchange data, set up the EPHY, and communicate
Maximum
Segment
(Meters)
Length
100
100
MC9S12NE64 Integrated Ethernet Controller, Rev. 0.2
Table 3. Summary of EPHY Compatibility
Manchester
4B/5B with
Encoding
Method
MLT-3
MC9S12NE64 Ethernet Physical Transceiver (EPHY)
Star
Star
Topology Media
Cat. 3, 4, 5
2 Pair UTP
2 Pair UTP
Cat. 5
(see
Figure
IEEE 802.3
Bit Rate
19.
(Mbps)
100
10
Figure 19
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