AN2692 Freescale Semiconductor / Motorola, AN2692 Datasheet - Page 33

• Manufacturer Part Number: AN2692
• Description: MC9S12NE64 Integrated Ethernet Controller
• Manufacturer: Freescale Semiconductor / Motorola

Figure 25
ensures that a capability is advertised during auto-negotiation. For example, if the user does not want to
allow a network device to ever negotiate to full-duplex operation at 100 Mbps using flow control, the user
could ensure that both the FLCTL and TAF_100FD bits are clear before enabling the EPHY clock
generation (if auto-negotiation is set).
Interrupt Control Register
The interrupt control register indicates which events would trigger an EPHY interrupt. An EPHY interrupt
is indicated by the EPHYIF bit in the EPHYSR register; a CPU interrupt is triggered only if the EPHYIEN
bit in the EPHYCTL0 bit is set. Also, when an EPHY interrupt occurs, a two-step interrupt-clearing
mechanism is required (as discussed in the
select PHY interrupt events is provided in this section. The interrupt control register is shown in
See the MC9S12NE64 data sheet for a complete description of all bits. Some interrupt control register
bits are described below:
Reading the interrupt control register (through the EMAC MII management interface) is an important part
of the clearing mechanism for the EPHYIF bit, but it is more important to decode which PHY interrupt
occurred and correctly handle these interrupt events.
Freescale Semiconductor
•
•
•
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Reset:
Read:
Write:
ACKIE (acknowledge bit received interrupt enable) and PRIE (page received interrupt enable) —
Indicate that the auto-negotiation process is exchanging base pages.
LCIE (link changed enable) — Occurs when the link changes meaning (either a new link has been
established, or an established link has been lost). To determine what has occurred after this
interrupt, the PHY status register and proprietary status register must be read and decoded
according to the
ANIE (auto-negotiation changed enable) — Occurs when the state of the auto-negotiation state
machine has changed since the last access of this register. A change to the auto-negotiation state
machine may require re-verification of the resolved auto-negotiation settings (see the
Register and Proprietary Status Register
PDFIE — Occurs when both auto-negotiation and parallel detection mechanisms for determining
a link partner’s ability fail.
shows the auto-negotiate advertisement register. Setting the bits for a particular Ethernet option
15
0
0
ACKIE
Figure 26. Interrupt Control Register (MII Management Register 16)
14
0
PRIE
13
0
PHY Status Register and Proprietary Status Register
LCIE
MC9S12NE64 Integrated Ethernet Controller, Rev. 0.2
12
0
ANIE
11
0
PDFIE
10
0
Clearing the EPHY Interrupt
RFIE
9
0
section).
JABIE
8
0
MC9S12NE64 Ethernet Physical Transceiver (EPHY)
0
7
0
ACKR
6
0
PGR
5
0
section). A brief discussion of
CNG
LNK
0
4
section.
CNG
AN
3
0
PDF
0
2
PHY Status
RMTF
Figure
1
0
JABI
0
0
26.
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