AN2692 Freescale Semiconductor / Motorola, AN2692 Datasheet - Page 30

• Manufacturer Part Number: AN2692
• Description: MC9S12NE64 Integrated Ethernet Controller
• Manufacturer: Freescale Semiconductor / Motorola

MC9S12NE64 Ethernet Physical Transceiver (EPHY)
is not accessible from the MC9S12NE64 register map. With auto-negotiation disabled, the speed and
duplex mode for the EPHY must be manually set using the MII management interface and writing to the
DPLX and DATARATE bits of the PHY control register (see
If auto-negotiation is used, the ANDIS bit in the EPHYCTL0 register should be cleared (alternatively, the
ANE bit of the EPHY PHY control register can be set through the MII). When the EPHY and EPHY clock
are enabled, the MC9S12NE64 will use auto-negotiation to determine speed, duplex mode, and flow
control settings. When auto-negotiation is complete, the device must ensure that the EMAC is also
configured to operate with the settings that the auto-negotiation process resolved. To determine the
resolved capabilities, the EPHY proprietary status register must be read using an EMAC MII read
operation and then decoded (see
EPHY Interrupt Enable
Before enabling the EPHY interrupts (by setting the EPHYIEN bit in the EPHYCTL0 register), the EPHY
PHY interrupt control register (see
not visible from the EMAC MII management interface (see the
Clearing the EPHY Interrupt
Figure 21
EPHY interrupt. Clearing an EPHY interrupt is a two-step process:
Reading an internal EPHY register through the MII management interface is performed by an MII read
operation by the EMAC. For an EMAC MII read operation, the user must provide a PHY address (PADDR)
and PHY register address (RADDR). After the MII read operation, the result of the MII read is stored in
the MRDATA register (see the
Internal EPHY Control and Status Registers
These registers are not directly accessible from the MC9S12NE64 register map. Using the EMAC MII
read and write operation will provide access to these internal EPHY registers. IEEE 802.3 specifies the
register set, which consists of 32 individual 16-bit PHY registers. The IEEE 802.3 specification refers to
these registers as the MII management register set (see IEEE 802.3, clause 22). IEEE 802.3 specifies
the contents of registers 0 through 15; registers 16 through 31 can be defined by the developer.
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•
•
Read the EPHY internal interrupt register (register 0x10) through the MII management interface
(MDIO)
Write the EPHYIP bit to 1
shows the Ethernet physical transceiver status register (EPHYSR), which is used to clear an
Reset:
Read:
Write:
Figure 21. Ethernet Physical Transceiver Status Register (EPHYSR)
Bit 7
0
0
MC9S12NE64 Integrated Ethernet Controller, Rev. 0.2
= Unimplemented
MII Management Interface
6
0
0
Figure
Figure
100DIS
26).
5
1
27) must be configured. The PHY interrupt control register is
10DIS
4
1
section).
3
0
0
Figure
Interrupt Control Register
22).
2
0
0
1
0
0
Freescale Semiconductor
EPHYIF
Bit 0
0
section).