EM639165 Etron Technology Inc., EM639165 Datasheet - Page 21
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EM639165
Manufacturer Part Number
EM639165
Description
8Mega x 16bits SDRAM
Manufacturer
Etron Technology Inc.
Datasheet
1.EM639165.pdf
(48 pages)
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Preliminary
[ Write Interrupted by Write ]
Burst write operation can be interrupted by new write of any bank. Random column access is allowed. WRITE to WRITE
interval is minimum 1 CLK.
[ Write Interrupted by Read ]
Burst write operation can be interrupted by read of the same or the other bank. Random column access is allowed. WRITE
to READ interval is minimum 1 CLK. The input data on DQ at the interrupting READ cycle is "don't care".
Command
Command
BA0,1
BA0,1
DQM
A0-9
A0-9
CLK
CLK
A10
A11
A10
A11
DQ
DQ
Write
Write
Dai0
Dai0
Y i
00
Y i
00
0
0
Write Interrupted by Write (CL=3,BL=4)
Write Interrupted by Read (CL=3,BL=4)
READ
Write
Daj0
00
Y j
00
Y j
0
0
Daj1
Write
Dbk0
Y k
10
0
Dbk1 Dbk2
Qaj0
21
Qaj1
Write
Dal0
Y l
00
0
Write
Dbk0 Dbk1
Dal1
Y k
10
0
Dal2
READ
Dal3
Y l
00
0
Rev 1.0
EM639165
Qal0
Feb. 2001