SSD1859 Solomon Systech, SSD1859 Datasheet - Page 14

• Manufacturer Part Number: SSD1859
• Description: 128 x 80 STN LCD Segment / Common 4 G/S Drive
• Manufacturer: Solomon Systech

R/ W ( WR )
E( RD )
7. FUNCTIONAL BLOCK DESCRIPTIONS
Command Decoder and Command Interface
This module determines whether the input data is interpreted as data or command. Data is directed to
this module based upon the input of the
RAM (GDDRAM). If
and written to the corresponding command register.
Reset is the same function as Power ON Reset (POR). Once
about 1us, all internal circuitry will be back to its initial status. Refer to Command Description section for
more information.
MPU Parallel 6800-series Interface
The parallel interface consists of 8 bi-directional data pins (D
R/ W ( WR )
status register.
Command Registers depending on the status of
latch signal (clock) when they are high and low respectively. Refer to Figure 10 and 11 of parallel timing
characteristics for Parallel Interface Timing Diagram of 6800-series microprocessors.
In order to match the operating frequency of display RAM with that of the microprocessor, pipeline
processing is internally performed which requires the insertion of a dummy read before the first actual
display data read. This is shown in Figure 3 below.
Data bus
MPU Parallel 8080-series interface
The parallel interface consists of 8 bi-directional data pins (D
read is controlled by
Refer to P.34, Figure 12 and 13 of parallel timing characteristics for Parallel Interface Timing Diagram of
8080-series microprocessor.
Similar to 6800-series interface, a dummy read is also required before the first actual display data read.
CS
Solomon Systech
input serves as data latch signal (clock) when it is low. Whether it is display data or status register
input High indicates a read operation from the Graphic Display Data RAM (GDDRAM) or the
write column address
R/ W ( WR )
N
Figure 3 - Display data read with the insertion of dummy read
D/ C
D/ C
.
is low, the input at D
input Low indicates a write operation to Display Data RAM or Internal
R/ W ( WR )
dummy read
and
D/ C
E( RD )
pin. If
0
-D
input indicate a write or read cycle when
D/ C
7
is interpreted as a Command and it will be decoded
D/ C
data read1
input. The
n
is high, data is written to Graphic Display Data
0
0
-D
-D
RES
Dec 2003
7
7
E( RD )
),
),
R/ W ( WR ), D/ C
R/ W ( WR )
data read 2
receives a negative reset pulse of
n+1
and
P 14/48 Rev 1.0
CS
,
E( RD )
input serves as data
,
E( RD )
,
data read 3
D/ C
n+2
CS
and
and
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is low.
CS
CS
SSD1859
.
. The