SSD1859 Solomon Systech, SSD1859 Datasheet - Page 15

• Manufacturer Part Number: SSD1859
• Description: 128 x 80 STN LCD Segment / Common 4 G/S Drive
• Manufacturer: Solomon Systech

MPU Serial 4-wire Interface
The serial interface consists of serial clock SCK, serial data SDA,
into a 8-bit shift register on every rising edge of SCK in the order of D
every eighth clock and the content in the shift register is written to the Display Data RAM or command
register in the same clock. No extra clock or command is required to end the transmission.
MPU Serial 3-wire Interface
Operation is similar to 4-wire serial interface except
command is used to indicate that a specified number display data byte (1-256) is to be transmitted. Next
byte after the display data string is handled as a command.
It should be noted that if there is a signal glitch at SCK that causing an out of synchronization in the
serial communication, a hardware reset pulse at
synchronization.
Modes of operation
Graphic Display Data RAM (GDDRAM)
The GDDRAM is a bit mapped static RAM holding the bit pattern to be displayed. The size of the RAM
is 128 x 81 x 2 = 20736bits. Figure 4 is a description of the GDDRAM address map. For mechanical
flexibility, remapping on both Segment and Common outputs are provided respectively. For vertical
scrolling of the display, an internal register storing the display start line can be set to control the portion
of the RAM data to be mapped to the display. Figure 4 shows the cases in which the display start line
register are set at 48H.
SSD1859
Data Read
Data Write
Command Read
Command Write
Rev 1.0
6800 parallel
Yes
Yes
Status only
Yes
P 15/48 Dec 2003
8080 parallel
Yes
Yes
Status only
Yes
RES
D/ C
pin is required to initialize the chip for re-
is not used. The Set Display Data Length
D/ C
7
, D
and
6
,...D
Serial
No
Yes
No
Yes
CS
0
.
. Input to SDA is shifted
D/ C
is sampled on
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