STV5730 ST Microelectronics, STV5730 Datasheet - Page 10

• Manufacturer Part Number: STV5730
• Description: MULTISTANDARD ON-SCREEN DISPLAY FOR VCR
• Manufacturer: ST Microelectronics

STV5730
1.4.4 - Position Register
HORIZONTAL POSITION
VERTICAL POSITION
1.4.5 - Mode Register
M0 : M0 = 0
M1 : M1 = 0
M2 : M2 = 0
M3 : M3 = 0
M4 : M4 = 0
M5 : M5 = 0
M6 : M6 = 0
M7 : M7 = 0
M8 : M8 = 0
M9 : This Mode bit has to be kept at a low level.
M10 : M10 = 0
M11 : M11 = 0
2 - THE MICROPROCESSOR SERIAL INTERFACE
The STV5730 is down loaded by the microprocessor through a three wire serial interface : DATA, CLK,
CSN. The CLK and CSN signals are internally ORed in order to validate the transfer when the STV5730 is
chip selected only (i.e. CSN = 0). The CSN rising edge validates the internal data transfer.
2.1 - Message Formats (see Figure 2)
16-bit, 8-bit and 0-bit formats are available. The 8-bit and 0-bit message formats may be useful to speed
up the STV5730 down loading.
This 16-bit address message loads the serial interface write pointer. This address is incremented after each
data message.
This 16-bit data message writes the data at the location indicated by the write pointer.
10/19
15
15
0
0
M11
11
11
M0 = 1
M1 = 1
M2 = 1
M3 = 1
M4 = 1
M5 = 1
M6 = 1
M7 = 1
M8 = 1
M10 = 1
M11 = 1
0
0
M10
10
0
0
VERTICAL POSITION
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
the BAR pin is disabled
the BAR pin has an action on the line PLL
the missing sync pulses are not detected
the missing sync pulses are detected
the MUTE pin is forced to 0
the MUTE pin delivers the internal MUTE signal
the MUTE time constant is 8 lines
the MUTE time constant is 32 lines
the sync is not re-inserted
the sync is re-inserted for improved text stability
the gain of pins VIDEO OUT1 & VIDEO OUT2 is 0dB.
the gain of pins VIDEO OUT1 & VIDEO OUT2 is 6dB.
the color encoder is enabled (PAL or NTSC)
the color encoder is disabled (B&W or SECAM)
the VIDEO OUT2 pin outputs the VIDEO IN signal
the VIDEO OUT2 pin outputs the composite sync
the VIDEO OUT2 pin is in high impedance state
the VIDEO OUT2 pin is in low impedance state
No delay compensation
It enables the delay compensation of the internal sync extractor.
The mute signal output is synchronized on vertical sync in order to limit its transitions.
The mute signal is not synchronized on vertical sync thus accelerating the VIDEO IN
presence detection (useful in full page mode).
12
12
0
1
M9
9
11
11
M8
8
BUF[11:8]
Any value from 6 to 63
Any value from 1 to 63
M7
7
8
M6
STRU[7:6]
6
6
7
DATA[11:0]
6
M5
5
5
5
0
M4
4
4
HORIZONTAL POSITION
M3
DEPL[4:0]
3
M2
2
0
0
M1
1
ADDRESS
DATA
M0
0
0