STV5730 ST Microelectronics, STV5730 Datasheet - Page 12

• Manufacturer Part Number: STV5730
• Description: MULTISTANDARD ON-SCREEN DISPLAY FOR VCR
• Manufacturer: ST Microelectronics

STV5730
2.2.1 - Address Map
PAGE
ROW ATTRIBUTES : STRU[7:6] = 11 - BUF[11:8] = 0 - DEPL[4:0] from 0 to 10
REGISTERS
2.3 - Initialization and Down-loading Sequence
It is important that the STV5730 is correctly reset
and initialized after the circuit is powered prior to
any writing. This routine is shown in Figure 3. The
two initialization bytes (00db 1000) must procede
the reset instruction (x2) every time it is transmitted.
Figure 3
3 - THE LINE LOCKED PLL
The PLL frequency is 504 * f
3.1 - Mixed Mode Behavior
In mixed mode, the internal PLL is line locked to the
incoming CVBS signal. The sync is either extracted
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Write
Set Control Registers
RESET & INITIALIZE
: ROW 0 : STRU[7:6] = 0 or 1 - BUF[11:8] = 0 - DEPL[4:0] from 0 to 27
: STRU[7:6] = 11 - BUF[11:8] = 0
Set RAM Attributes
Set Row Attributes
ROW 1 : STRU[7:6] = 0 or 1 - BUF[11:8] = 1 - DEPL[4:0] from 0 to 27
.........
ROW 10 : STRU[7:6] = 0 or 1 - BUF[11:8] = 10 - DEPL[3:0] from 0 t0 27
DEPL[4:0] = 12 for ZOOM register, 13 for COLOR register,
i.e. TEXT PAGE
* Write Pointer
* Data
* etc.
* Zoom
* Color
* Control
* Position
* Mode
* 0 to 10
3000H
3000H
00dbH
1000H
STOP
H
= 7.875MHz.
: .................
14 for CONTROL register, 15 for POSITION register,
16 for MODE register
by the STV5730 (if C7 control bit is set) or provided
by the application in a composite form on the
CSYNC pin (if C7 control bit is cleared). The
STV5730 separates the vertical sync from the com-
posite synchronism.
The STV5730 PLL features built-in protection
mechanisms against missing and parasitichorizon-
tal sync pulses. These mechanisms are activated
once the loop is locked.
The STV5730 PLL is also insensitive to the head
switching disturbing the synchronism in the VTR
applications (playback).
The missing pulses may be detected.The M1mode
bit enables the detection.
In addition, the BAR input pin is available to enter
a signal that forces the PLL in free run mode. This
capability may be used for search mode in VTRs,
to improve the loop robustness against the noise
bar. The BAR input is enabled by the M0 mode bit.
3.2 - Horizontal Sync Re-insertion
This mechanism is of interest in mixed mode, to
cancel the text horizontal jitter when the sync signal
is too bad. It is activated by the M4 mode bit and
must be turned off in full page mode.
The active part of the line is protected against
parasitic sync insertion. The modified sync is active
on all output pins (ie CSYNC if C7 is set, VIDEO
OUT1, VIDEO OUT2).
A jitter greater than 0.42usec cannot be cancelled.
An ease use of the synchronism re-insertion capa-
bility is to have it always active in mixed mode.
3.3 - Full Page Mode Behavior
In this case, the PLL is locked on an internal64usec
reference derived from the 4*fsc quartz.
The STV5730 generates a non interlace output.
4 - MUTE
The STV5730 monitors the sync to determine
whether it is a stable signal or not.
MUTE = high : no stable signal
MUTE = low : stable CVBS input signal
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