LM3S8933 Luminary Micro, Inc, LM3S8933 Datasheet - Page 29

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LM3S8933

Manufacturer Part Number
LM3S8933
Description
Lm3s8933 Arm Microcontroller
Manufacturer
Luminary Micro, Inc
Datasheet

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July 25, 2008
I
GPIOs
Power
2
C
Configurable for output to: drive an output pin, generate an interrupt, or initiate an ADC sample
sequence
Compare external pin input to external pin input or to internal programmable voltage reference
Master and slave receive and transmit operation with transmission speed up to 100 Kbps in
Standard mode and 400 Kbps in Fast mode
Interrupt generation
Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing
mode
6-36 GPIOs, depending on configuration
5-V-tolerant input/outputs
Programmable interrupt generation as either edge-triggered or level-sensitive
Low interrupt latency; as low as 6 cycles and never more than 12 cycles
Bit masking in both read and write operations through address lines
Can initiate an ADC sample sequence
Pins configured as digital inputs are Schmitt-triggered.
Programmable control for GPIO pad configuration:
On-chip Low Drop-Out (LDO) voltage regulator, with programmable output user-adjustable
from 2.25 V to 2.75 V
Hibernation module handles the power-up/down 3.3 V sequencing and control for the core
digital logic and analog circuits
Low-power options on controller: Sleep and Deep-sleep modes
Low-power options for peripherals: software controls shutdown of individual peripherals
Weak pull-up or pull-down resistors
2-mA, 4-mA, and 8-mA pad drive for digital communication; up to four pads can be
configured with an 18-mA pad drive for high-current applications
Slew rate control for the 8-mA drive
Open drain enables
Digital input enables
Preliminary
LM3S8933 Microcontroller
29

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