LM3S2620 Luminary Micro, Inc, LM3S2620 Datasheet - Page 16

• Manufacturer Part Number: LM3S2620
• Description: Lm3s2620 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Table of Contents
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Synchronous Serial Interface (SSI) ............................................................................................ 307
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
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Register 21:
Inter-Integrated Circuit (I
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
16
UART Line Control (UARTLCRH), offset 0x02C ............................................................... 283
UART Control (UARTCTL), offset 0x030 ......................................................................... 285
UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 287
UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 289
UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 291
UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 292
UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 293
UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 295
UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 296
UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 297
UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 298
UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 299
UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 300
UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 301
UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 302
UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 303
UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 304
UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 305
UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 306
SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 319
SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 321
SSI Data (SSIDR), offset 0x008 ...................................................................................... 323
SSI Status (SSISR), offset 0x00C ................................................................................... 324
SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 326
SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 327
SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 329
SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 330
SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 331
SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 332
SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 333
SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 334
SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 335
SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 336
SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 337
SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 338
SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 339
SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 340
SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 341
SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 342
SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 343
I
I
I
I
I
I
2
2
2
2
2
2
C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 358
C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 359
C Master Data (I2CMDR), offset 0x008 ......................................................................... 363
C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... 364
C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... 365
C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 366
2
C) Interface ........................................................................................ 344
Preliminary
July 25, 2008