LM3S2620 Luminary Micro, Inc, LM3S2620 Datasheet - Page 398

• Manufacturer Part Number: LM3S2620
• Description: Lm3s2620 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Reset
Reset
Type
Type
Controller Area Network (CAN) Module
CAN Bit Timing (CANBIT)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x00C
Type R/W, reset 0x0000.2301
398
Bit/Field
31:15
14:12
reserved
11:8
7:6
RO
RO
31
15
0
0
R/W
Register 4: CAN Bit Timing (CANBIT), offset 0x00C
This register is used to program the bit width and bit quantum. Values are to be programmed to the
system clock frequency. This register is write-enabled by the CCE and INIT bits in the CANCTL
register. See “Bit Time and Bit Rate” on page 386 for more information.
RO
30
14
0
0
TSeg2
R/W
reserved
RO
29
13
0
1
TSeg2
TSeg1
Name
SJW
R/W
RO
28
12
0
0
R/W
RO
27
11
0
0
Type
R/W
R/W
R/W
RO
R/W
RO
26
10
0
0
TSeg1
0x0000
Reset
R/W
0x2
0x3
0x0
RO
25
0
9
1
Preliminary
R/W
RO
24
0
8
1
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Time Segment after Sample Point
0x00-0x07: The actual interpretation by the hardware of this value is
such that one more than the value programmed here is used.
So, for example, a reset value of 0x2 defines that there is 3(2+1) bit
time quanta defined for Phase_Seg2 (see Figure 15-2 on page 387).
The bit time quanta is defined by BRP.
Time Segment Before Sample Point
0x00-0x0F: The actual interpretation by the hardware of this value is
such that one more than the value programmed here is used.
So, for example, the reset value of 0x3 defines that there is 4(3+1) bit
time quanta defined for Phase_Seg1 (see Figure 15-2 on page 387).
The bit time quanta is define by BRP.
(Re)Synchronization Jump Width
0x00-0x03: The actual interpretation by the hardware of this value is
such that one more than the value programmed here is used.
During the start of frame (SOF), if the CAN controller detects a phase
error (misalignment), it can adjust the length of TSeg2 or TSeg1 by the
value in SJW. So the reset value of 0 adjusts the length by 1 bit time
quanta.
reserved
R/W
RO
23
0
7
0
SJW
R/W
RO
22
0
6
0
R/W
RO
21
0
5
0
R/W
RO
20
0
4
0
R/W
RO
19
0
3
0
BRP
R/W
RO
18
0
2
0
July 25, 2008
R/W
RO
17
0
1
0
R/W
RO
16
0
0
1