LM3S2730 Luminary Micro, Inc, LM3S2730 Datasheet - Page 42

• Manufacturer Part Number: LM3S2730
• Description: Lm3s2730 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Interrupts
42
a. 0 is the default priority for all the settable priorities.
Table 4-2. Interrupts
Exception Type
Bus Fault
Usage Fault
-
SVCall
Debug Monitor
-
PendSV
SysTick
Interrupts
Vector Number
24-33
0-15
16
17
18
19
20
21
22
23
34
35
36
37
38
39
40
41
42
43
44
45
Vector
Number
16 and
above
7-10
12
13
14
15
11
5
6
Interrupt Number (Bit in
Interrupt Registers)
Priority
settable
settable
settable
settable
settable
settable
settable
-
-
8-17
18
19
20
21
22
23
24
25
26
27
28
29
0
1
2
3
4
5
6
7
-
a
Preliminary
Description
Pre-fetch fault, memory access fault, and other address/memory related
faults. This is synchronous when precise and asynchronous when
imprecise.
You can enable or disable this fault.
Usage fault, such as undefined instruction executed or illegal state
transition attempt. This is synchronous.
Reserved.
System service call with SVC instruction. This is synchronous.
Debug monitor (when not halting). This is synchronous, but only active
when enabled. It does not activate if lower priority than the current
activation.
Reserved.
Pendable request for system service. This is asynchronous and only
pended by software.
System tick timer has fired. This is asynchronous.
Asserted from outside the ARM Cortex-M3 core and fed through the
NVIC (prioritized). These are all asynchronous. Table 4-2 on page 42
lists the interrupts on the LM3S2730 controller.
Description
Processor exceptions
GPIO Port A
GPIO Port B
GPIO Port C
GPIO Port D
GPIO Port E
UART0
Reserved
SSI0
Reserved
Watchdog timer
Timer0 A
Timer0 B
Timer1 A
Timer1 B
Timer2 A
Timer2 B
Analog Comparator 0
Analog Comparator 1
Reserved
System Control
Flash Control
July 25, 2008