LM3S310 Luminary Micro, Inc, LM3S310 Datasheet - Page 106

• Manufacturer Part Number: LM3S310
• Description: Lm3s310 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

General-Purpose Input/Outputs (GPIOs)
8.2.2
8.2.3
106
Figure 8-3. GPIODATA Write Example
During a read, if the address bit associated with the data bit is set to 1, the value is read. If the
address bit associated with the data bit is set to 0, it is read as a zero, regardless of its actual
value. For example, reading address GPIODATA + 0x0C4 yields as shown in Figure 8-4.
Figure 8-4. GPIODATA Read Example
Data Direction
The GPIO Direction (GPIODIR) register (see page 112) is used to configure each individual pin as
an input or output.
Interrupt Operation
The interrupt capabilities of each GPIO port are controlled by a set of seven registers. With these
registers, it is possible to select the source of the interrupt, its polarity, and the edge properties.
When one or more GPIO inputs cause an interrupt, a single interrupt output is sent to the interrupt
controller for the entire GPIO port. For edge-triggered interrupts, software must clear the interrupt
to enable any further interrupts. For a level-sensitive interrupt, it is assumed that the external
source holds the level constant for the interrupt to be recognized by the controller.
Three registers are required to define the edge or sense that causes interrupts:
Interrupts are enabled/disabled via the GPIO Interrupt Mask (GPIOIM) register (see page 116).
When an interrupt condition occurs, the state of the interrupt signal can be viewed in two locations:
the GPIO Raw Interrupt Status (GPIORIS) and GPIO Masked Interrupt Status (GPIOMIS)
registers (see pages 117 and 118). As the name implies, the GPIOMIS register only shows
interrupt conditions that are allowed to be passed to the controller. The GPIORIS register indicates
that a GPIO pin meets the conditions for an interrupt, but has not necessarily been sent to the
controller.
GPIO Interrupt Sense (GPIOIS) register (see page 113)
GPIO Interrupt Both Edges (GPIOIBE) register (see page 114)
GPIO Interrupt Event (GPIOIEV) register (see page 115)
Returned Value
GPIODATA
ADDR[9:2]
ADDR[9:2]
GPIODATA
0x0C4
0x098
0xEB
Preliminary
0
1
9
0
1
0
9
u
7
7
8
0
1
0
0
0
6
u
8
6
7
1
1
1
1
5
1
7
1
5
6
1
1
1
4
0
0
6
u
4
5
0
1
0
3
0
1
5
u
3
4
0
1
0
2
1
0
4
0
2
3
0
1
0
1
1
1
3
1
1
2
1
0
0
0
0
1
2
u
0
1
0
1
0
0
0
0
0
July 5, 2006