LM3S310 Luminary Micro, Inc, LM3S310 Datasheet - Page 53

• Manufacturer Part Number: LM3S310
• Description: Lm3s310 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

6.1.4.5
6.1.5
6.2
July 5, 2006
changes above. It is the user's responsibility to have a stable clock source (like the main oscillator)
before the RCC register is switched to use the PLL.
Clock Verification Timers
There are three identical clock verification circuits that can be enabled though software. The circuit
checks the faster clock by a slower clock using timers:
If the verification timer function is enabled and a failure is detected, the main clock tree is
immediately switched to a working clock and an interrupt is generated to the controller. Software
can then determine the course of action to take. The actual failure indication and clock switching
does not clear without a write to the CLKVCLR register, an external reset, or a POR reset. The
clock verification timers are controlled by the PLLVER, IOSCVER, and MOSCVER bits in the RCC
register (see page 76).
System Control
For power-savings purposes, the RCGCn, SCGCn, and DCGCn registers control the clock gating
logic for each peripheral or block in the system while the controller is in Run, Sleep, and
Deep-Sleep mode, respectively. The DC1, DC2 and DC4 registers act as a write mask for the
RCGCn, SCGCn, and DCGCn registers.
In Run mode, the controller is actively executing code. In Sleep mode, the clocking of the device is
unchanged but the controller no longer executes code (and is no longer clocked). In Deep-Sleep
mode, the clocking of the device may change (depending on the Run mode clock configuration)
and the controller no longer executes code (and is no longer clocked). An interrupt returns the
device to Run mode from one of the sleep modes; the sleep modes are entered on request from
the code.
Initialization and Configuration
The PLL is configured using direct register writes to the Run-Mode Clock Configuration (RCC)
register. The steps required to successfully change the PLL-based system clock are:
1.
2.
3.
4.
5.
Important:
The main oscillator checks the PLL.
The main oscillator checks the internal oscillator.
The internal oscillator divided by 64 checks the main oscillator.
Bypass the PLL and system clock divider by setting the BYPASS bit and clearing the USESYS
bit in the RCC register. This configures the system to run off a “raw” clock source (using the
main oscillator or internal oscillator) and allows for the new PLL configuration to be validated
before switching the system clock to the PLL.
Select the crystal value (XTAL) and oscillator source (OSCSRC), and clear the PWRDN and OE
bits in RCC. Setting the XTAL field automatically pulls valid PLL configuration data for the
appropriate crystal, and clearing the PWRDN and OE bits powers and enables the PLL and its
output.
Select the desired system divider (SYSDIV) and set the USESYS bit in RCC. The SYSDIV field
determines the system frequency for the microcontroller.
Wait for the PLL to lock by polling the PLLLRIS bit in the Raw Interrupt Status (RIS) register.
If the PLL doesn’t lock, the configuration is invalid.
Enable use of the PLL by clearing the BYPASS bit in RCC.
If the BYPASS bit is cleared before the PLL locks, it is possible to render the device
unusable.
Preliminary
LM3S310 Data Sheet
53