LM3S310 Luminary Micro, Inc, LM3S310 Datasheet - Page 81
LM3S310
Manufacturer Part Number
LM3S310
Description
Lm3s310 Arm Microcontroller
Manufacturer
Luminary Micro, Inc
Datasheet
1.LM3S310.pdf
(336 pages)
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July 5, 2006
Reset
Reset
Type
Type
Bit/Field
XTAL to PLL Translation (PLLCFG)
Offset 0x064
31:16
15:14
RO
RO
31
15
0
-
13:5
4:0
OD
Register 18: XTAL to PLL Translation (PLLCFG), offset 0x064
This register provides a means of translating external crystal frequencies into the appropriate PLL
settings. This register is initialized during the reset sequence and updated anytime that the XTAL
field changes in the Run-Mode Clock Configuration (RCC) register (see page 76).
RO
RO
30
14
0
-
reserved
Name
OD
R
RO
RO
F
29
13
0
-
RO
RO
28
12
0
-
Type
RO
RO
27
11
RO
RO
RO
RO
0
-
RO
RO
26
10
0
-
Reset
RO
RO
25
F
0
9
-
0
Preliminary
-
-
-
RO
RO
24
0
8
-
reserved
Description
Reserved bits return an indeterminate value, and should
never be changed.
This field specifies the value supplied to the PLL’s OD input.
This field specifies the value supplied to the PLL’s F input.
This field specifies the value supplied to the PLL’s R input.
RO
RO
23
0
7
-
RO
RO
22
0
6
-
RO
RO
21
0
5
-
RO
RO
20
0
4
-
RO
RO
19
0
3
-
LM3S310 Data Sheet
RO
RO
18
0
2
-
R
RO
RO
17
0
1
-
RO
RO
16
0
0
-
81
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