LM3S317 Luminary Micro, Inc, LM3S317 Datasheet - Page 56

• Manufacturer Part Number: LM3S317
• Description: Lm3s317 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

System Control
6.2
6.3
Table 6-1. System Control Register Map
56
Device Identification and Capabilities
Local Control
Offset
0x01C
0x000
0x004
0x008
0x010
0x014
0x018
0x030
Name
DID0
DID1
DC0
DC1
DC2
DC3
DC4
PBORCTL
hardware brings the system clock back to the source and frequency it had at the onset of
Deep-Sleep mode before enabling the clocks that were stopped during the Deep-Sleep duration.
Initialization and Configuration
The PLL is configured using direct register writes to the Run-Mode Clock Configuration (RCC)
register. The steps required to successfully change the PLL-based system clock are:
1.
2.
3.
4.
5.
Important:
Register Map
Table 6-1 lists the System Control registers, grouped by function. The offset listed is a
hexadecimal increment to the register’s address, relative to the System Control base address of
0x400FE000.
Bypass the PLL and system clock divider by setting the BYPASS bit and clearing the USESYS
bit in the RCC register. This configures the system to run off a “raw” clock source (using the
main oscillator or internal oscillator) and allows for the new PLL configuration to be validated
before switching the system clock to the PLL.
Select the crystal value (XTAL) and oscillator source (OSCSRC), and clear the PWRDN and OEN
bits in RCC. Setting the XTAL field automatically pulls valid PLL configuration data for the
appropriate crystal, and clearing the PWRDN and OEN bits powers and enables the PLL and its
output.
Select the desired system divider (SYSDIV) and set the USESYS bit in RCC. The SYSDIV field
determines the system frequency for the microcontroller.
Wait for the PLL to lock by polling the PLLLRIS bit in the Raw Interrupt Status (RIS) register.
If the PLL doesn’t lock, the configuration is invalid.
Enable use of the PLL by clearing the BYPASS bit in RCC.
If the BYPASS bit is cleared before the PLL locks, it is possible to render the device
unusable.
0x3F3F01FF
0x00007FFD
0x001171BF
0x000F0007
0x0000001F
0x01070011
Reset
-
-
Type
R/W
Preliminary
RO
RO
RO
RO
RO
RO
RO
Description
Device identification 0
Device identification 1
Device capabilities 0
Device capabilities 1
Device capabilities 2
Device Capabilities 3
Device Capabilities 4
Power-On and Brown-Out Reset Control
February 6, 2007
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