LM3S317 Luminary Micro, Inc, LM3S317 Datasheet - Page 80

• Manufacturer Part Number: LM3S317
• Description: Lm3s317 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

System Control
80
Bit/Field
19:17
16:14
13
12
11
PWMDIV
reserved
BYPASS
PWRDN
Name
OEN
Type
R/W
R/W
R/W
R/W
RO
Reset
0x7
0
1
1
1
Preliminary
Description
PWM Unit Clock Divisor
This field specifies the binary divisor used to predivide the
system clock down for use as the timing reference for the
PWM module. This clock is only power 2 divide and rising
edge is synchronous without phase shift from the system
clock.
Reserved bits return an indeterminate value, and should
never be changed.
PLL Power Down
This bit connects to the PLL PWRDN input. The reset value
of 1 powers down the PLL. See Table 6-4 on page 82 for
PLL mode control.
PLL Output Enable
This bit specifies whether the PLL output driver is enabled.
If cleared, the driver transmits the PLL clock to the output.
Otherwise, the PLL clock does not oscillate outside the PLL
module.
Note:
PLL Bypass
Chooses whether the system clock is derived from the PLL
output or the OSC source. If set, the clock that drives the
system is the OSC source. Otherwise, the clock that drives
the system is the PLL output clock divided by the system
divider.
Note:
Value
000
001
010
100
101
011
110
111
Both PWRDN and OEN must be cleared to run the
PLL.
The ADC module must be clocked from the PLL or
directly from a 14-MHz to an 18-MHz clock source
in order to operate properly.
WriterNote: See issue 2799 on this
note--it may need clarification.
Divisor
/2
/4
/8
/16
/32
/64
/64
/64 (default)
February 6, 2007