LM3S317 Luminary Micro, Inc, LM3S317 Datasheet - Page 62
![no-image](/images/no-image-200.jpg)
LM3S317
Manufacturer Part Number
LM3S317
Description
Lm3s317 Arm Microcontroller
Manufacturer
Luminary Micro, Inc
Datasheet
1.LM3S317.pdf
(376 pages)
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System Control
62
Reset
Reset
Type
Type
Bit/Field
31:21
19:17
15:12
11:8
Device Capabilities 1 (DC1)
Offset 0x010
20
16
7
6
5
4
3
RO
RO
31
15
0
0
Register 4: Device Capabilities 1 (DC1), offset 0x010
This register is predefined by the part and can be used to verify features.
MINSYSDIV
RO
RO
30
14
0
1
MAXADCSPD
MINSYSDIV
reserved
reserved
reserved
PWM
TEMP
Name
ADC
WDT
MPU
PLL
RO
RO
29
13
0
1
a
a
a
RO
RO
28
12
0
1
a
RO
RO
27
11
0
0
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
reserved
MAXADCSPD
RO
RO
26
10
0
0
RO
RO
25
Reset
0
9
0
0x07
Preliminary
0x1
0
1
0
1
1
0
1
1
1
RO
RO
24
0
8
1
Description
Reserved bits return an indeterminate value, and should
never be changed.
A 1 in this bit indicates the presence of the PWM module.
Reserved bits return an indeterminate value, and should
never be changed.
A 1 in this bit indicates the presence of the ADC module.
The reset value is hardware-dependent. A value of 0x7
specifies a 25-MHz clock with a PLL divider of 8. See the
RCC register (page 78) for how to change the system clock
divisor using the SYSDIV bit.
This field indicates the maximum rate at which the ADC
samples data. A value of 0x1 indicates 250K samples per
second.
This bit indicates whether the Memory Protection Unit
(MPU) in the Cortex-M3 is available. A 0 in this bit indicates
the MPU is not available; a 1 indicates the MPU is
available.
See the ARM® Cortex™-M3 Technical Reference Manual
for details on the MPU.
Reserved bits return an indeterminate value, and should
never be changed.
This bit specifies the presence of an internal temperature
sensor.
A 1 in this bit indicates the presence of an implemented
PLL in the device.
A 1 in this bit indicates a watchdog timer on the device.
MPU
RO
RO
23
0
7
1
reserved
RO
RO
22
0
6
0
TEMP
RO
RO
21
0
5
1
PWM
PLL
RO
RO
20
1
4
1
WDT
RO
RO
19
0
3
1
reserved
SWO
RO
RO
18
0
2
1
February 6, 2007
SWD
RO
RO
17
0
1
1
JTAG
ADC
RO
RO
16
1
0
1
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