XC2V8000-5BF957C Xilinx, Inc., XC2V8000-5BF957C Datasheet - Page 13

• Manufacturer Part Number: XC2V8000-5BF957C
• Description: Virtex-II 1.5V Field-Programmable Gate Array
• Manufacturer: Xilinx, Inc.

Virtex-II 1.5V Field-Programmable Gate Arrays
nected to the same voltage. This voltage is determined by
the output standards in use.
Within a bank, output standards can be mixed only if they
use the same V
dards. GTL and GTLP appear under all voltages because
their open-drain outputs do not depend on V
Some input standards require a user-supplied threshold
voltage, V
matically configured as inputs for the V
imately one in six of the I/O pins in the bank assume this
role.
Module 2 of 4
6
Figure 7: Virtex-II I/O Banks: Top View for Wire-Bond
Figure 8: Virtex-II I/O Banks: Top View for Flip-Chip
Table 6
REF
lists compatible input standards.
. In this case, certain user-I/O pins are auto-
Packages (CS, FG, & BG)
CCO
Packages (FF & BF)
.
Bank 1
Bank 4
Bank 0
Bank 5
Table 5
lists compatible output stan-
Bank 0
Bank 5
Bank 1
Bank 4
ug002_c2_014_112900
REF
ds031_66_112900
voltage. Approx-
CCO
.
www.xilinx.com
1-800-255-7778
V
consequently only one V
each bank. However, for correct operation, all V
the bank must be connected to the external reference volt-
age source.
Table 5: Compatible Output Standards
The V
device pinout tables. Within a given package, the number of
V
device. In larger devices, more I/O pins convert to V
pins. Since these are always a superset of the V
used for smaller devices, it is possible to design a PCB that
permits migration to a larger device if necessary.
All V
nected to the V
devices, some V
nect within the package. These unconnected pins can be
left unconnected externally, or, if necessary, they can be
connected to the V
larger device.
V
3.3 V
2.5 V
1.8 V
1.5 V
REF
REF
1.2V
CCO
REF
pins within a bank are interconnected internally, and
CCO
and V
pins for the largest device anticipated must be con-
PCI, LVTTL, SSTL3 (I & II), AGP-2X, LVDS_33,
LVDSEXT_33, LVCMOS33, LVDCI_33,
LVDCI_DV2_33, SSTL3_DCI (I & II), LVPECL,
GTL, GTLP
SSTL2 (I & II), LVCMOS25, GTL, GTLP,
LVDS_25, LVDSEXT_25, LVDCI_25,
LVDCI_DV2_25, SSTL2_DCI (I & II), LDT,
ULVDS, BLVDS
LVCMOS18, GTL, GTLP, LVDCI_18,
LVDCI_DV2_18
HSTL (I, II, III, & IV), LVCMOS15, GTL, GTLP,
LVDCI_15, LVDCI_DV2_15, GTLP_DCI,
HSTL_DCI (I,II, III & IV)
GTL_DCI
and the V
CCO
REF
CCO
pins can vary depending on the size of
voltage and not used for I/O. In smaller
CCO
pins used in larger devices do not con-
REF
Compatible Standards
voltage to permit migration to a
pins for each bank appear in the
REF
DS031-2 (v1.8) October 12, 2001
Advance Product Specification
voltage can be used within
REF
REF
pins in
pins
REF
R