XC2V8000-5BF957C Xilinx, Inc., XC2V8000-5BF957C Datasheet - Page 31
XC2V8000-5BF957C
Manufacturer Part Number
XC2V8000-5BF957C
Description
Virtex-II 1.5V Field-Programmable Gate Array
Manufacturer
Xilinx, Inc.
Datasheet
1.XC2V8000-5BF957C.pdf
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Virtex-II 1.5V Field-Programmable Gate Arrays
2. “READ_FIRST”
The “READ_FIRST” option is a read-before-write mode.
The same clock edge that writes data input (DI) into the memory also transfers the prior content of the memory cell
addressed into the data output registers DO, as shown in
3. “NO_CHANGE”
The “NO_CHANGE” option maintains the content of the output registers, regardless of the write operation. The clock edge
during the write mode has no effect on the content of the data output register DO. When the port is configured as
“NO_CHANGE”, only a read operation loads a new value in the output register DO, as shown in
Module 2 of 4
24
RAM Contents
RAM Contents
Data_out
Data_out
Address
Address
Data_in
Data_in
Data_in
Data_in
CLK
CLK
WE
WE
Figure 32: NO_CHANGE Mode
Figure 31: READ_FIRST Mode
DI
DI
New
New
Old
Old
aa
aa
Internal
Internal
Memory
Memory
www.xilinx.com
1-800-255-7778
Figure
Last Read Cycle Content (no change)
DO
DO
31.
Prior stored data
No change during write
New
New
Old
DS031_13_102000
DS031_12_102000
DS031-2 (v1.8) October 12, 2001
Advance Product Specification
Figure
32.
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