XC2V8000-5BF957C Xilinx, Inc., XC2V8000-5BF957C Datasheet - Page 9

• Manufacturer Part Number: XC2V8000-5BF957C
• Description: Virtex-II 1.5V Field-Programmable Gate Array
• Manufacturer: Xilinx, Inc.

Virtex-II 1.5V Field-Programmable Gate Arrays
Table 2: Supported Differential Signal I/O Standards
All of the user IOBs have fixed-clamp diodes to V
ground. The IOBs are not compatible or compliant with 5 V
I/O standards (not 5 V tolerant).
Table 3
trolled Impedance. See
(DCI), page
Table 3: Supported DCI I/O Standards
Module 2 of 4
2
Notes:
1.
2.
LVPECL_33
LDT_25
LVDS_33
LVDS_25
LVDSEXT_33
LVDSEXT_25
BLVDS_25
ULVDS_25
LVDCI_33
LVDCI_DV2_33
LVDCI_25
LVDCI_DV2_25
LVDCI_18
LVDCI_DV2_18
LVDCI_15
LVDCI_DV2_15
GTL_DCI
GTLP_DCI
HSTL_I_DCI
HSTL_II_DCI
HSTL_III_DCI
HSTL_IV_DCI
SSTL2_I_DCI
SSTL2_II_DCI
SSTL3_I_DCI
SSTL3_II_DCI
Standard
LVDCI_XX and LVDCI_DV2_XX are LVCMOS controlled
impedance buffers, matching the reference resistors or half
of the reference resistors.
These are SSTL compatible.
Standard
I/O
I/O
lists supported I/O standards with Digitally Con-
(1)
(1)
(1)
(1)
9.
(2)
(2)
(2)
(2)
(1)
(1)
(1)
(1)
Output
V
3.3
2.5
3.3
2.5
3.3
2.5
2.5
2.5
CCO
Output
V
3.3
3.3
2.5
2.5
1.8
1.8
1.5
1.5
1.2
1.5
1.5
1.5
1.5
1.5
2.5
2.5
3.3
3.3
CCO
Digitally Controlled Impedance
Input
V
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
CCO
Input
V
3.3
3.3
2.5
2.5
1.8
1.8
1.5
1.5
1.2
1.5
1.5
1.5
1.5
1.5
2.5
2.5
3.3
3.3
CCO
Input
V
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
REF
Input
V
0.75
0.75
1.25
1.25
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0.8
1.0
0.9
0.9
1.5
1.5
REF
0.430 - 0.670
0.250 - 0.400
0.250 - 0.400
0.330 - 0.700
0.330 - 0.700
0.250 - 0.450
0.430 - 0.670
Termination
to 1.22 V
490 mV
Output
CCO
Series
Series
Series
Series
Series
Series
Series
Series
Single
Single
Single
Single
V
Type
Split
Split
Split
Split
Split
Split
OD
and to
www.xilinx.com
1-800-255-7778
Logic Resources
IOB blocks include six storage elements, as shown in
Figure
Each storage element can be configured either as an
edge-triggered D-type flip-flop or as a level-sensitive latch.
On the input, output, and 3-state path, one or two DDR reg-
isters can be used.
Double data rate is directly accomplished by the two regis-
ters on each path, clocked by the rising edges (or falling
edges) from two different clock nets. The two clock signals
are generated by the DCM and must be 180 degrees out of
phase, as shown in
and 3-state data signals, each being alternately clocked out.
2.
OCK2
OCK2
OCK1
OCK1
Reg
Reg
Reg
Reg
Figure 2: Virtex-II IOB Block
DDR mux
DDR mux
Figure
3-State
Output
3. There are two input, output,
DS031-2 (v1.8) October 12, 2001
Advance Product Specification
IOB
ICK1
ICK2
Reg
Reg
Input
PAD
DS031_29_100900
R