MT16D832M-6X Micron, MT16D832M-6X Datasheet - Page 2

• Manufacturer Part Number: MT16D832M-6X
• Description: DRAM Module, EDO DRAM, 32MByte Density, 5V Supply, SIMM Package
• Manufacturer: Micron

NOT RECOMMENDED FOR NEW DESIGNS
GENERAL DESCRIPTION
accessed, 16MB and 32MB solid-state memories orga-
nized in a x32 configuration. During READ or WRITE
cycles, each bit is uniquely addressed through 22 ad-
dress bits that are entered 11 bits (A0-A10) at a time.
RAS# is used to latch the first 11 bits and CAS# the latter
11 bits. READ and WRITE cycles are selected with the
WE# input. A logic HIGH on WE# dictates read mode,
while a logic LOW on WE# dictates write mode. During
a WRITE cycle, data-in (D) is latched by the falling edge
of CAS#. Since WE# goes LOW prior to CAS# going LOW,
the output pin(s) remain open (High-Z) until the next
CAS# cycle.
FAST PAGE MODE
erations (READ or WRITE) within a row-address-de-
fined page boundary. The FAST-PAGE-MODE cycle is
always initiated with a row address strobed in by RAS#,
followed by a column address strobed in by CAS#. Ad-
ditional columns may be accessed by providing valid
column addresses, strobing CAS# and holding RAS#
LOW, thus executing faster memory cycles. Returning
RAS# HIGH terminates the FAST-PAGE-MODE opera-
tion.
EDO PAGE MODE
an accelerated FAST-PAGE-MODE cycle. The primary
advantage of EDO is the availability of data-out even
after CAS# goes back HIGH. EDO provides for CAS#
JEDEC-DEFINED
PRESENCE-DETECT –
MT8D432(X) (16MB)
4, 8 Meg x 32 DRAM SIMMs
DM44_2.p65 – Rev. 9/98
SYMBOL
PRD1
PRD2
PRD3
PRD4
The MT8D432(X) and MT16D832(X) are randomly
FAST-PAGE-MODE operations allow faster data op-
EDO PAGE MODE, designated by the “X” version, is
PIN
67
68
69
70
-5*
V
V
V
NC
SS
SS
SS
V
NC
NC
NC
-6
SS
2
precharge time (
going invalid. This elimination of CAS# output control
provides for pipelined READs.
turned the output buffers off (High-Z) with the rising
edge of CAS#. EDO operates like FAST-PAGE-MODE
READs, except data will be held valid or become valid
after CAS# goes HIGH, as long as RAS# and OE# are
held LOW. (Refer to the MT4C4M4E8 DRAM data sheet
for additional information on EDO functionality.)
REFRESH
memory cycle and decreases chip current to a reduced
standby level. Also, the chip is preconditioned for the
next cycle during the RAS# HIGH time. Memory cell
data is retained in its correct state by maintaining
power and executing any RAS# cycle (READ, WRITE) or
RAS# REFRESH cycle (RAS#-ONLY, CBR or HIDDEN) so
that all 2,048 combinations of RAS# addresses are ex-
ecuted at least every 32ms, regardless of sequence.
The CBR REFRESH cycle will invoke the refresh counter
for automatic RAS# addressing.
x16 CONFIGURATION
CAS# pins must be connected together (DQ1 to DQ17,
DQ2 to DQ18 and so forth, and CAS0# to CAS2# and
CAS1# to CAS3#). Each RAS# is then a bank select for
the x16 memory organization.
JEDEC-DEFINED
PRESENCE-DETECT –
MT16D832(X) (32MB)
*EDO version only
SYMBOL
PRD1
PRD2
PRD3
PRD4
FAST-PAGE-MODE modules have traditionally
Returning RAS# and CAS# HIGH terminates a
For x16 applications, the corresponding DQ and
Micron Technology, Inc., reserves the right to change products or specifications without notice.
PIN
67
68
69
70
t
CP) to occur without the output data
-5*
NC
V
V
V
SS
SS
SS
4, 8 MEG x 32
DRAM SIMMs
NC
V
NC
NC
-6
SS
©1998, Micron Technology, Inc.