MT16LSDT12864AG-133 Micron, MT16LSDT12864AG-133 Datasheet - Page 11

• Manufacturer Part Number: MT16LSDT12864AG-133
• Description: 1GB SDRAM UDIMM
• Manufacturer: Micron

Figure 6:
Burst Type
CAS Latency
PDF: 09005aef8088b2e3/Source: 09005aef8088077a
SD8_16C64_128x64AG.fm - Rev. C 6/05 EN
CAS Latency Diagram
COMMAND
COMMAND
Accesses within a given burst may be programmed to be either sequential or interleaved;
this is referred to as the burst type and is selected via bit M3.
The ordering of the accesses within a burst is determined by the burst length, the burst
type, and the starting column address, as shown in Table 6 on page 10.
The CAS latency is the delay, in clock cycles, between the registration of a READ com-
mand and the availability of the first piece of output data. The latency can be set to two
or three clocks.
If a READ command is registered at clock edge n, and the latency is m clocks, the data
will be available by clock edge n + m. The DQ will start driving as a result of the clock
edge one cycle earlier (n + m - 1), and provided that the relevant access times are met,
the data will be valid by clock edge n + m. For example, assuming that the clock cycle
time is such that all relevant access times are met, if a READ command is registered at T0
and the latency is programmed to two clocks, the DQ will start driving after T1 and the
data will be valid by T2, as shown in Figure 6. Table 7 on page 12, indicates the operating
frequencies at which each CAS latency setting can be used.
Reserved states should not be used as unknown operation or incompatibility with future
versions may result.
CLK
CLK
DQ
DQ
READ
READ
T0
T0
512MB (SR), 1GB (DR): (x64) 168-Pin SDRAM UDIMM
CAS Latency = 2
NOP
NOP
T1
T1
11
t
t AC
LZ
CAS Latency = 3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T2
NOP
T2
NOP
t
t AC
D
LZ
t OH
OUT
Mode Register Definition
T3
T3
NOP
D
t OH
OUT
DON’T CARE
UNDEFINED
©2002 Micron Technology, Inc. All rights reserved.
T4