MT16LSDT6464 Micron, MT16LSDT6464 Datasheet - Page 16

• Manufacturer Part Number: MT16LSDT6464
• Description: 168-Pin SDRAM DIMMs (x64)
• Manufacturer: Micron

32, 64 Meg x 64 SDRAM DIMMs
SD8_16C32_64x64AG_B.p65–Rev. B, Pub. 8/01
NOTES
1. All voltages referenced to V
2. This parameter is sampled. V
3. I
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to
6. An initial pause of 100µs is required after power-
7. AC characteristics assume
8. In addition to meeting the transition rate specifi-
9. Outputs measured at 1.5V with equivalent load:
10.
11. AC timing and I
12. Other input signals are allowed to transition no
13. I
f = 1 MHz, T
Specified values are obtained with minimum cycle
time and the outputs open.
indicate cycle time at which proper operation over
the full temperature range is ensured (0°C
+70°C).
up, followed by two AUTO REFRESH commands,
before proper device operation is ensured. (V
and V
and V
REFRESH command wake-ups should be repeated
any time the
cation, the clock and CKE must transit between V
and V
manner.
t
the open circuit condition; it is not a reference to
V
t
with timing referenced to 1.5V crossover point. If
the input transition time is longer than 1 ns, then
the timing is referenced at V
and no longer at the 1.5V crossover point.
more than once every two clocks and are otherwise
at valid V
erly initialized.
HZ defines the time at which the output achieves
OH before going High-Z.
DD
DD
OH
specifications are tested after the device is prop-
is dependent on output loading and cycle rates.
or V
SS
DD
IL
Q must be at same potential.) The two AUTO
Q must be powered up simultaneously. V
(or between V
OL
IH
. The last valid data element will meet
or V
A
t
REF refresh requirement is exceeded.
= 25°C; pin under test biased at 1.4V.
Q
IL
DD
levels.
tests have V
IL
and V
t
T = 1ns.
SS
IL
.
(MAX) and V
IL
IH
DD
50pF
= 0V and V
) in a monotonic
, V
DD
Q = +3.3V;
IH
IH
(MIN)
= 3V,
T
A
DD
IH
SS
16
14. Timing actually specified by
15. Timing actually specified by
16. Timing actually specified by
17. Required clocks are specified by JEDEC function-
18. The I
19. Address transitions average one transition every
20. CLK must be toggled a minimum of two times dur-
21. Based on
22. V
23. The clock frequency must remain constant (stable
24. Auto precharge mode only. The precharge timing
25. Precharge mode only.
26. JEDEC and PC100 specify three clocks.
27.
28. Parameter guaranteed by design.
29. The value of
30. For -10E, CL= 2 and
31. CKE is HIGH during refresh command period
fied as a reference only at minimum cycle rate.
specified as a reference only at minimum cycle rate.
ality and are not dependent on any timing param-
eter.
tionally according to the amount of frequency al-
teration for the test condition.
two clocks.
ing this period.
133 and -13E.
width
than one third of the cycle rate. V
(MIN) = -2V for a pulse width
clock is defined as a signal cycling within timing
constraints specified for the clock pin) during ac-
cess or precharge states (READ, WRITE, including
t
used to reduce the data rate.
budget (
7ns for -10E after the first clock delay, after the last
WRITE is executed. May not exceed limit set for
precharge mode.
t
is guaranteed by design.
SPDs is calculated from
t
t
ally a nominal value and does not result in a fail
value.
WR, and PRECHARGE commands). CKE may be
AC for -133/-13E at CL = 3 with no load is 4.6ns and
CK = 7.5ns; for -13E, CL = 2 and
RFC (MIN) else CKE is LOW. The I
IH
overshoot: V
DD
3ns, and the pulse width cannot be greater
t
current will increase or decrease propor-
RP) begins 7ns for -13E; 7.5ns for -133 and
t
CK = 10ns for -10E, and
168-PIN SDRAM DIMMs
t
RAS. use in -13E speed grade module
256MB / 512MB (x64)
IH
(MAX) = V
t
CK = 10ns; for -133, CL = 3 and
t
RC -
t
t
WR plus
DD
t
WR.
t
CKS; clock(s) speci-
RP = 45ns.
3ns.
Q + 2V for a pulse
t
IL
CK = 7.5ns.
DD
t
CK = 7.5ns for -
undershoot: V
©2001, Micron Technology, Inc.
6 limit is actu-
t
RP; clock(s)
IL