MT16LSDT6464AG-13E Micron, MT16LSDT6464AG-13E Datasheet - Page 10

• Manufacturer Part Number: MT16LSDT6464AG-13E
• Description: DRAM Module, SDRAM, 512MByte Density, 3.3V Supply, DIMM Package
• Manufacturer: Micron

COMMANDS
able commands. This is followed by written descrip-
tion of each command. For a more detailed description
TRUTH TABLE – SDRAM Commands and DQMB Operation
(Note: 1; notes appear below table)
NOTE: 1. CKE is HIGH for all commands shown except SELF REFRESH.
32, 64 Meg x 64 SDRAM DIMMs
SD8_16C32_64x64AG_B.p65–Rev. B, Pub. 8/01
NAME (FUNCTION)
COMMAND INHIBIT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE burst)
BURST TERMINATE
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or
SELF REFRESH (Enter self refresh mode)
LOAD MODE REGISTER
Write Enable/Output Enable
Write Inhibit/Output High-Z
The Truth Table provides a quick reference of avail-
2. A0-A11 define the op-code written to the mode register,.and A12 should be driven LOW
3. A0-A12 provide row address, and BA0, BA1 determine which device bank is made active.
4. A0-A9 provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW disables
5. A10 LOW: BA0, BA1 determine which device bank is being precharged. A10 HIGH: all device banks are precharged and
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay).
the auto precharge feature; BA0, BA1 determine which device bank is being read from or written to.
BA0, BA1 are “Don’t Care.”
10
CS# RAS# CAS# WE# DQMB
H
L
L
L
L
L
–
–
L
L
L
of commands and operations, refer to the 256Mb
SDRAM component data sheet.
H
X
H
H
H
L
L
L
L
–
–
H
H
H
H
X
L
L
L
L
–
–
168-PIN SDRAM DIMMs
256MB / 512MB (x64)
H
H
H
H
X
L
–
L
L
L
–
L/H
L/H
H
X
X
X
X
X
X
X
L
8
8
Bank/Row
Bank/Col
Bank/Col Valid
Op-code
ADDR
Code
X
X
X
X
–
–
©2001, Micron Technology, Inc.
High-Z
Active
Active
DQs NOTES
ADVANCE
X
X
X
X
X
X
X
6, 7
3
4
4
5
2
8
8