MT18LD1672AGF-5 X Micron, MT18LD1672AGF-5 X Datasheet - Page 13
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MT18LD1672AGF-5 X
Manufacturer Part Number
MT18LD1672AGF-5 X
Description
64Mb EDO/FPM - OBSOLETE
Manufacturer
Micron
Datasheet
1.MT18LD1672AGF-5_X.pdf
(28 pages)
NOTES: (continued)
8, 16, 32 Meg x 72 Buffered DRAM DIMMs
DM77_2.p65 – Rev. 3/00
19.
20. A +2ns (MIN) and a +5ns (MAX) timing skew from the DRAM to the module resulted from the addition of line drivers.
21.
22. Requires that
23. The
24. A -2ns (MIN) and a -5ns (MAX) timing skew from the DRAM to the module resulted from the addition of line drivers.
25. The
26. Column address changed once each cycle.
27. Either
28. RAS#-ONLY REFRESH requires that all rows be refreshed at least once every 64ms (4,096 rows for the 4K version and
t
V
t
to reading valid up-level on subsequent DIMM position.
than the specified
applied). With or without the
than the specified
applied). With or without the
8,192 rows for the 8K version). CBR REFRESH requires that at least 4,096 cycles be completed every 64ms.
OFF (MAX) defines the time at which the output achieves the open circuit condition and is not referenced to V
PDOFF (MAX) is determined by the pullup resistor value. Care must be taken to ensure adequate recovery time prior
OL
.
t
t
RAD (MAX) limit is no longer specified.
RCD (MAX) limit is no longer specified.
t
RCH or
t
AA and
t
RRH must be satisfied for a READ cycle.
t
t
RAD (MAX) limit, then access time was controlled exclusively by
RCD (MAX) limit, then access time was controlled exclusively by
t
CAC are not violated.
t
t
RAD (MAX) limit,
RCD (MAX) limit,
t
t
RCD (MAX) was specified as a reference point only. If
RAD (MAX) was specified as a reference point only. If
t
t
AA and
AA,
13
t
RAC and
t
CAC must always be met.
t
Micron Technology, Inc., reserves the right to change products or specifications without notice.
CAC must always be met.
BUFFERED DRAM DIMMs
8, 16, 32 MEG x 72
t
t
CAC (
AA (
t
RAC and
t
RAC [MIN] no longer
t
CAC no longer
t
t
RCD was greater
RAD was greater
©2000, Micron Technology, Inc.
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