MT18LSDT3272 Micron, MT18LSDT3272 Datasheet - Page 10

• Manufacturer Part Number: MT18LSDT3272
• Description: 168-Pin SDRAM DIMMs (x72) ECC Registered
• Manufacturer: Micron

16, 32, 64 Meg x 72 PC133/PC100 Registered SDRAM DIMMs
SD18C16_32_64x72G_B.p65 – Pub. 11/01
NOTE: 1. CKE is HIGH for all commands shown except SELF REFRESH.
COMMANDS
able commands. This is followed by a written descrip-
tion of each command. For a more detailed description
TRUTH TABLE – SDRAM COMMANDS AND DQMB OPERATION
(Note: 1, notes appear below table)
NAME (FUNCTION)
COMMAND INHIBIT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE burst)
BURST TERMINATE
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or
SELF REFRESH (Enter self refresh mode)
LOAD MODE REGISTER
Write Enable/Output Enable
Write Inhibit/Output High-Z
The Truth Table provides a quick reference of avail-
2. A0-A11 (128MB/256MB), A0-A12 (512MB) define the op-code written to the Mode Register, and should be driven low.
3. A0-A11 (128MB/256MB), A0-A12 (512MB) provide device row address. BA0, BA1 determine which device bank is made
4. A0-A9 provide device column address for 128MB module; A0-A9/A11 for 256MB and 512MB modules; A10 HIGH enables
5. A10 LOW: BA0, BA1 determine which device bank is being precharged. A10 HIGH: both device banks are precharged and
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay).
active.
the auto precharge feature (nonpersistent), while A10 LOW disables the auto precharge feature; BA0, BA1 determine
which device bank is being read from or written to.
BA0, BA1 are “Don’t Care.”
10
C S # R A S #C A S # W E # D Q M B A D D R
168-PIN REGISTERED SDRAM DIMM
128MB / 256MB / 512MB (x72, ECC)
H
L
L
L
L
L
L
–
–
L
L
of commands and operations refer to the 64Mb, 128Mb,
or 256Mb SDRAM datasheets.
H
H
H
H
X
L
L
L
L
–
–
H
H
H
X
H
L
L
–
–
L
L
Micron Technology, Inc., reserves the right to change products or specifications without notice.
H
H
H
H
X
L
L
L
L
–
–
L/H
L/H
X
X
X
X
H
X
X
X
L
8
8
Bank/Row
Bank/Col
Bank/Col Valid
Op-Code
Code
X
X
X
X
–
–
High-Z
©2001, Micron Technology, Inc.
Active
Active
D Q s NOTES
X
X
X
X
X
X
X
6, 7
3
4
4
5
2
8
8