MT9085BPR Zarlink Semiconductor, Inc., MT9085BPR Datasheet - Page 15
![no-image](/images/no-image-200.jpg)
MT9085BPR
Manufacturer Part Number
MT9085BPR
Description
1024 Channels TDM (ST-BUS) to Parallel Bus Access Circuit (PAC)
Manufacturer
Zarlink Semiconductor, Inc.
Datasheet
1.MT9085BPR.pdf
(20 pages)
AC Electrical Characteristics
Figure 15)
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25
1
2
C16i
CKD=0
DFPo
DFPo
CFPo
CKD=1
DFPo
DFPo
CFPo
ST-BUS Frame Boundary
Established by F0i
Data - Memory Frame Pulse
Delay
Connection - Memory Frame
Pulse Delay
- Voltages are with respect to Ground (V
Characteristics
64 C16
Cycles
t
t
DFPo
DFPo
°
C and are for design aid only: not guaranteed and not subject to production testing.
t
t
DFPo
DFPo
Figure 15 - DFPo and CFPo Output Timing
†
- Data Memory and Connect Memory Frame Pulse (See
t
t
Sym
t
DFPo
CFPo
CFPD
SS
) unless otherwise stated.
t
CFPo
Min
0
0
Typ
71 C16 Cycles
t
CFPD
‡
Max
37
30
Units
ST-BUS Frame Boundary
ns
ns
68 C16
Cycles
Established by F0i
t
CFPo
C
C
L
L
=85 pF
=85 pF
t
t
64 C16
DFPo
DFPo
Cycles
Test Conditions
MT9085B
t
t
DFPo
DFPo
2-139