MT90870 Zarlink Semiconductor, Inc., MT90870 Datasheet - Page 2

• Manufacturer Part Number: MT90870
• Description: Flexible 12k Digital Switch (F12kDX)
• Manufacturer: Zarlink Semiconductor, Inc.

MT90870
The device contains two connection memory blocks, one for the Backplane output and one for the Local output.
Data to be output on the serial streams may come from either of the data memories (Connection Mode) or
directly from the connection memory contents (Message Mode).
In Connection Mode the contents of the connection memory defines, for each output stream and channel, the
source stream and channel (stored in data memory) to be switched.
In Message Mode, microprocessor data can be written to the connection memory for broadcast on the output
streams on a per channel basis. This feature is useful for transferring control and status information to external
circuits or other ST-BUS devices.
The device uses a master frame pulse (FP8i) and master clock (C8i) to define the frame boundary and timing
for both the Backplane port and the Local port. The device will automatically detect whether an ST-BUS or a
GCI-BUS style frame pulse is being used. There is a two frame delay from the time RESET is de-asserted to
the establishment of full switch functionality. During this period the frame format is determined before switching
begins.
The device provides FP8o, FP16o, C8o and C16o outputs to support external devices connected to the Local
port.
A non-multiplexed Motorola microprocessor port allows programming of the various device operation modes
and switching configurations. The microprocessor port provides access for Register read/write, Connection
Memory read/write and Data Memory read-only operations. The port has a 15-bit address bus, 16-bit data bus
and 4 control signals. The microprocessor may monitor channel data in the Backplane and Local data
memories.
The mandatory requirements of the IEEE-1149.1 (JTAG) standard are fully supported via a dedicated test port.
2
BSTo0-31
BCST0-3
BSTi0-31
BORS
FP8i
C8i
Backplane
Interface
Timing Unit
Backplane
V
PLL
DD_PLL
Figure 1 - MT90870 Functional Block Diagram
Connection Memory
(8,192 locations)
V
DD_IO
Backplane
DS CS R/W A14-A0 DTA D15-D0
V
DD_CORE
Backplane Data Memories
Microprocessor Interface
and Internal Registers
Local Data Memories
(4,096 channels)
(8,192 channels)
V
SS (GND)
Connection Memory
(4,096 locations)
Local
RESET
TMS
ODE
TDI TDO TCK TRST
Preliminary Information
Test Port
Timing
Local
Unit
Interface
Interface
Local
Local
LSTo0-15
LCST0-1
LSTi0-15
LORS
FP8o
FP16o
C8o
C16o