MT8967 Zarlink Semiconductor, Inc., MT8967 Datasheet - Page 5

• Manufacturer Part Number: MT8967
• Description: Integrated CODEC with A-Law companding and CCITT PCM encoding (20 pin PDIP-SOIC)
• Manufacturer: Zarlink Semiconductor, Inc.

V
An external voltage must be supplied to the V
which provides the reference voltage for the digital
encoding and decoding of the analog signal. For
V
overload (maximum analog signal detect level) is
equal to an analog input V
version) or 2.5V (A-Law version) and is equivalent to
a signal level of 3.17 dBm0 or 3.14 dBm0
respectively, at the codec.
The analog output voltage from the decoder at V
defined as:
µ -Law:
V
A-Law:
V
V
where C = chord number (0-7)
V
capacitive load of up to 40 pF.
The recommended reference voltage for the MT8960
series of codecs is 2.5V ±0.5%. The output voltage
from the reference source should have a maximum
temperature coefficient of 100 ppm/C°. This voltage
should have a total regulation tolerance of ±0.5%
both for changes in the input voltage and output
loading of the voltage reference source. A voltage
reference
specifications is shown in Figure 5. Analog Devices
’AD1403A voltage reference circuit is capable of
Ref
Ref
Ref
Ref
Ref
Ref
X
X
X
= 2.5V, the digital encode decision value for
is a high impedance input with a varying
S = step number (0-15)
[(
[(
[(
+5V
2
circuit
128
128
2
C+1
-0.5
128
C
)(
)(
)
16.5 + S
+
capable
0.5 + S
(
128
32
32
NC
2
8
1
C
)(
AD1403A
)]
)]
NC
7
2
IN
of
2.5V
16.5 + S
± V
± V
Figure 5 - Typical Voltage Reference Circuit
= 2.415V ( µ -Law
NC
33
6
3
OFFSET
OFFSET
meeting
ISO
)]
NC
NC
5
4
2
C=0
C≠0
-CMOS
± V
OFFSET
Ref
these
R
pin
is
MT8960/61/62/63/64/65/66/67
driving a large number of codecs due to the high
input impedance of the V
precautions should be taken in PCB layout design to
minimize noise coupling to this pin.
capacitor connected from V
as close as possible to the codec is recommended to
minimize noise entering through V
should have good high frequency characteristics.
Timing
The codec operates in a synchronous manner (see
Figure 9a).
positive edge of C2i after F1i has gone
digital output at DSTo (which is a three-state output
driver) will then change from a high impedance state
to the sign bit of the encoded PCM word to be
output. This will remain valid until the next positive
edge, when the next most significant bit will be
output.
On the first negative clock edge (after F1i signal has
been internally synchronized and CA is at GNDD or
V
into the input shift register as the sign bit of the
incoming PCM word.
The eight-bit word is thus input at DSTi on negative
edges of C2i and output at DSTo on positive edges
of C2i.
F1i must return to a high level after the eighth
clock pulse causing DSTo to enter high impedance
and preventing further input data to DSTi. F1i will
continue to be sampled on every positive edge of
C2i. (Note: F1i may subsequently be taken low
during the same sampling frame to enable entry of
serial data into CSTi. This occurs usually mid-frame,
in conjunction with CA=V
control word into Register B. In this case, PCM input
and output are inhibited by CA at V
EE
) the logic signal present at DSTi will be clocked
The codec is activated on the first
0.1 µF
V
DD
Ref
FILTER/CODEC
, in order to enter an 8-bit
Ref
MT8960-67
to ground and located
Ref
Ref
DD
input.
. This capacitor
.)
A 0.1 µF
low.
Normal
The
6-23