CS4294 Cirrus Logic, CS4294 Datasheet - Page 14

• Manufacturer Part Number: CS4294
• Description: SoundFusion Audio/Docking Codec 97 (AMC 97)
• Manufacturer: Cirrus Logic

5.3.3
WD[15:0]
5.3.4
PD[19:0]
5.3.5
GP[9:0]
5.4 AC-Link Audio Input Frame
5.4.1
Codec Ready
Slot 1 Valid Tag
Slot 2 Valid Tag
Slot [3:11] Valid Tag
Slot 12 Valid Tag
14
WD15 WD14 WD13 WD12 WD11 WD10 WD9 WD8 WD7 WD6 WD5 WD4 WD3 WD2 WD1 WD0
PD19 PD18 PD17 PD16 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
Bit 19
Bit 19
Bit 19
Codec
Ready
Bit 15
In the serial data input frame, data is passed on the SDATA_IN pin FROM the CS4294 to the AC ’97
Controller. The data format for the input frame is very similar to the output frame. Figure 9 illustrates
the serial port timing.
18
18
18
Slot 1
Valid
Register Write Data (Slot 2)
Playback Data (Slots 3-11)
GPIO Data (Slot12)
Serial Data Input Slot Tag Bits (Slot 0)
14
Codec register data for write operations. For read operations, this data is ignored. If R/W# = 0, data must
be valid in both the Register Address (Slot 1) and the Register Write Data (Slot 2) during a frame when
the Slot [1:2] Valid = 11 or either SCRA[1:0] bit is set. Splitting the register address and the write data
across multiple frames is not permitted.
20-bit PCM playback (2’s complement) data for the left and right DACs. Any PCM data from the Con-
troller less than 20 bits should be left justified in the slot and zero-padded. Table 8 on page 28 lists the
definition of each respective slot. The mapping of a given slot is determined by the MD[1:0] bits found
in the AC Mode Control (Index 5Eh) register.
GPIO Output Data. Output data is transferred to the GPIO pins every frame in Slot 12.
Indicates the readiness of the CS4294’s AC-link and Control and Status registers. Immediately after a
Cold Reset this bit will be clear. Once the CS4294’s clocks and voltages are stable, this bit will be set.
Until the Codec Ready bit is set, no AC-link transactions should be attempted by the Controller. The
Codec Ready bit does not indicate readiness of the DACs, ADCs, Vref, or any other analog function.
Those must be checked in the Power Down Control/Status (Index 26h), Extended Audio Stat/Ctrl (Index
2Ah), and Extended Codec Stat/Ctrl (Index 3Eh) registers by the Controller before any access is made
to the mixer registers. Any accesses to the Codec while Codec Ready is clear is ignored.
Indicates Slot 1 contains a valid read back address.
Indicates Slot 2 contains valid register read data.
Indicates Slot [3:11] contains valid capture data from the Codec’s ADC.
Indicates Slot 12 contains valid read data of the GPIO Pin Status Register (Index 54h).
17
17
17
Slot 2
Valid
13
16
16
16
Slot 3
Valid
12
15
15
15
Slot 4
Valid
14
14
11
14
GP9 GP8 GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0
13
13
Slot 5
Valid
10
13
12
12
Slot 6
Valid
12
9
11
11
11
Slot 7
Valid
10
10
8
10
Slot 8
Valid
9
9
7
9
8
8
Slot 9
Valid
6
8
7
7
Slot 10
Valid
5
7
6
6
Slot 11
Valid
4
6
5
5
Slot 12
Valid
4
4
5
3
3
3
4
2
3
2
2
CS4294
1
DS326PP4
2
1
1
1
0
0
0
0