CS4294 Cirrus Logic, CS4294 Datasheet - Page 27

• Manufacturer Part Number: CS4294
• Description: SoundFusion Audio/Docking Codec 97 (AMC 97)
• Manufacturer: Cirrus Logic

6.1.25 GPIO Pin Configuration (Index 4Ch)
GC[9:0]
Default
6.1.26 GPIO Pin Polarity/Type Configuration (Index 4Eh)
GP[9:0]
6.1.27 GPIO Pin Sticky (Index 50h)
GS[8:3]
DS326PP4
Default
Default
D15
D15
D15
0
1
After a cold reset, power up, or extended codec register reset (see Extended Codec ID (Index 3Ch))
all GPIO pins are configured as inputs.
When the GPIO pin is defined as an input, its status is reported in the GPIO Pin Status (Index 54h)
register as well as Slot 12.
If a GPIO is defined as “sticky” the input requires a transition of the GPIO input pin to set the corre-
sponding bit in Slot 12 and the GPIO Pin Status (Index 54h) register. When “sticky” is set the corre-
sponding bit in GPIO Pin Polarity/Type Configuration (Index 4Ah) register determines which edge
of the GPIO pin will set GI[x]. If GP[x] is set, a low to high transition sets the GI[x] bit. A high to
low transition sets GI[x] if GP[x] is clear. Once set, writing a 0 to GI[x] will clear the “sticky” input.
D14
D14
D14
0
1
GPIO Pin Configuration. When set defines the corresponding GPIO pin as an input
03FFh
GPIO Pin Configuration. The definition of GP[8:3] changes based on the pin defined as an input or an
output by GC[8:3] of GPIO Pin Configuration (Index 4Ch).
FFFFh
GPIO Pin Sticky. If set, the GPIO pin input is latched.
0000h
GCx
D13
D13
D13
0
0
1
1
0
1
D12
D12
D12
0
1
D11
D11
D11
GPx
0
1
0
1
0
1
Table 7. GPIO Input/Output Configuration
D10
D10
D10
0
1
Function
res
res
D9
D9
D9
Output
Output
Input
Input
GC8
GP8
GS8
D8
D8
D8
GC7
GP7
GS7
D7
D7
D7
GC6
GP6
GS6
D6
D6
D6
Active High (default)
GC5
GP5
GS5
D5
D5
D5
CMOS drive
Open drain
Active Low
GC4
GP4
GS4
D4
D4
D4
GC3
GP3
GS3
D3
D3
D3
res
res
D2
D2
D2
CS4294
res
res
D1
D1
D1
res
res
D0
D0
D0
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